Line 28... |
Line 28... |
/* */
|
/* */
|
/* Author(s): */
|
/* Author(s): */
|
/* - Olivier Girard, olgirard@gmail.com */
|
/* - Olivier Girard, olgirard@gmail.com */
|
/* */
|
/* */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/* $Rev: 19 $ */
|
/* $Rev: 111 $ */
|
/* $LastChangedBy: olivier.girard $ */
|
/* $LastChangedBy: olivier.girard $ */
|
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
|
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
|
/*===========================================================================*/
|
/*===========================================================================*/
|
|
|
.global main
|
.global main
|
|
|
|
.set DMEM_BASE, (__data_start )
|
|
.set DMEM_200, (__data_start+0x00)
|
|
.set DMEM_250, (__data_start+0x50)
|
|
|
.set BCSCTL1, 0x0057
|
.set BCSCTL1, 0x0057
|
.set BCSCTL2, 0x0058
|
.set BCSCTL2, 0x0058
|
|
|
.set IE1, 0x0000
|
.set IE1, 0x0000
|
.set IFG1, 0x0002
|
.set IFG1, 0x0002
|
Line 51... |
Line 55... |
|
|
main:
|
main:
|
|
|
/* ------- WATCHDOG TEST INTERVAL MODE /64 - SMCLK /2 ------ */
|
/* ------- WATCHDOG TEST INTERVAL MODE /64 - SMCLK /2 ------ */
|
|
|
mov #0x0250, r1 ;# Initialize stack & Enable interrupts
|
mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
|
eint
|
eint
|
bis.b #0x01, &IE1
|
bis.b #0x01, &IE1
|
|
|
mov.b #0x02, &BCSCTL2 ;# SMCLK = MCLK/2
|
mov.b #0x02, &BCSCTL2 ;# SMCLK = MCLK/2
|
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
|
mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter
|
Line 67... |
Line 71... |
mov #0x1000, r15
|
mov #0x1000, r15
|
|
|
|
|
/* ------- WATCHDOG TEST INTERVAL MODE /64 - ACLK ------ */
|
/* ------- WATCHDOG TEST INTERVAL MODE /64 - ACLK ------ */
|
|
|
mov #0x0250, r1 ;# Initialize stack & Enable interrupts
|
mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts
|
eint
|
eint
|
bis.b #0x01, &IE1
|
bis.b #0x01, &IE1
|
|
|
mov.b #0x00, &BCSCTL1 ;# ACLK = LFXTCLK/1
|
mov.b #0x00, &BCSCTL1 ;# ACLK = LFXTCLK/1
|
mov #0x5a1f, &WDTCTL ;# Enable interval mode /64 & clear counter
|
mov #0x5a1f, &WDTCTL ;# Enable interval mode /64 & clear counter
|