OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.s43] - Diff between revs 111 and 134

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 111 Rev 134
Line 28... Line 28...
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $Rev: 134 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
.global main
.global main
 
 
.set   DMEM_BASE, (__data_start     )
.set   DMEM_BASE, (__data_start     )
Line 63... Line 63...
 
 
        mov.b   #0x02, &BCSCTL2	  ;# SMCLK = MCLK/2
        mov.b   #0x02, &BCSCTL2	  ;# SMCLK = MCLK/2
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
        mov   #0x0001, r15
        mov   #0x0001, r15
 
 
        mov   #0x0170, r14
        mov   #0x0470, r14
        call  #WAIT_FUNC
        call  #WAIT_FUNC
 
 
        mov   #0x1000, r15
        mov   #0x1000, r15
 
        mov.b   #0x00, &BCSCTL2	  ;# SMCLK = MCLK
 
 
 
 
        /* -------   WATCHDOG TEST INTERVAL MODE /64 - ACLK        ------ */
        /* -------   WATCHDOG TEST INTERVAL MODE /64 - ACLK        ------ */
 
 
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.