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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.v] - Diff between revs 134 and 180

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Rev 134 Rev 180
Line 28... Line 28...
/*                                                                           */
/*                                                                           */
/* Author(s):                                                                */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* $Rev: 134 $                                                                */
/* $Rev: 180 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $          */
/*===========================================================================*/
/*===========================================================================*/
 
 
`define LONG_TIMEOUT
`define LONG_TIMEOUT
 
 
integer mclk_counter;
integer mclk_counter;
Line 63... Line 63...
      @(negedge mclk);
      @(negedge mclk);
      mclk_counter = 0;
      mclk_counter = 0;
      r5_counter   = 0;
      r5_counter   = 0;
      repeat(1024) @(negedge mclk);
      repeat(1024) @(negedge mclk);
      if (mclk_counter !== 1024)        tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 =====");
      if (mclk_counter !== 1024)        tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 =====");
   `ifdef ASIC
   `ifdef ASIC_CLOCKING
     `ifdef WATCHDOG_MUX
     `ifdef WATCHDOG_MUX
        `ifdef SMCLK_DIVIDER
        `ifdef SMCLK_DIVIDER
            if (r5_counter   !== 7)     tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 =====");
            if (r5_counter   !== 7)     tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 =====");
        `else
        `else
            if (r5_counter   !== 14)    tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 =====");
            if (r5_counter   !== 14)    tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 =====");
Line 100... Line 100...
      @(negedge mclk);
      @(negedge mclk);
      mclk_counter = 0;
      mclk_counter = 0;
      r5_counter   = 0;
      r5_counter   = 0;
      repeat(7815) @(negedge mclk);
      repeat(7815) @(negedge mclk);
      if (mclk_counter !== 7815)         tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 =====");
      if (mclk_counter !== 7815)         tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 =====");
   `ifdef ASIC
   `ifdef ASIC_CLOCKING
     `ifdef WATCHDOG_MUX
     `ifdef WATCHDOG_MUX
            if (r5_counter      !== 4)   tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 =====");
            if (r5_counter      !== 4)   tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 =====");
     `else
     `else
        `ifdef WATCHDOG_NOMUX_ACLK
        `ifdef WATCHDOG_NOMUX_ACLK
           `ifdef LFXT_DOMAIN
           `ifdef LFXT_DOMAIN

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