Line 28... |
Line 28... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $ */
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/* $Rev: 134 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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`define LONG_TIMEOUT
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`define LONG_TIMEOUT
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initial
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initial
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Line 43... |
Line 43... |
$display("| START SIMULATION |");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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stimulus_done = 0;
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`ifdef WATCHDOG
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// WATCHDOG TEST: RD/WR ACCESS
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// WATCHDOG TEST: RD/WR ACCESS
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15==16'h1000);
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@(r15==16'h1000);
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if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 =====");
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`ifdef NMI
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if (r5 !== 16'h69d7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69d3 =====");
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`ifdef WATCHDOG_MUX
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if (r6 !== 16'h6955) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6951 =====");
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if (r4 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
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if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 =====");
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if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 1) =====");
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if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 =====");
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if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 1) =====");
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if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 1) =====");
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if (r8 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
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`else
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`ifdef WATCHDOG_NOMUX_ACLK
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if (r4 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
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if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 2) =====");
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if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 2) =====");
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if (r7 !== 16'h69a6) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a6 (CONFIG 2) =====");
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if (r8 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
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`else
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if (r4 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
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`ifdef ASIC
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if (r5 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) =====");
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if (r6 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) =====");
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if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) =====");
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`else
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if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 3) =====");
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if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 3) =====");
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if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3) =====");
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`endif
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if (r8 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
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`endif
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`endif
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`else
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`ifdef WATCHDOG_MUX
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if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
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if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 4) =====");
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if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 4) =====");
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if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 4) =====");
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if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
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`else
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`ifdef WATCHDOG_NOMUX_ACLK
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if (r4 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
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if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 5) =====");
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if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 5) =====");
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if (r7 !== 16'h6986) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6986 (CONFIG 5) =====");
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if (r8 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
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`else
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if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
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`ifdef ASIC
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if (r5 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) =====");
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if (r6 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) =====");
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if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) =====");
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`else
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if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 6) =====");
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if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 6) =====");
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if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6) =====");
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`endif
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if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
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`endif
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`endif
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`endif
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`ifdef NMI
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if (r9 !== 16'h0010) tb_error("====== WATCHDOG RD/WR ACCESS: IFG1 != 0x10 =====");
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`else
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if (r9 !== 16'h0000) tb_error("====== WATCHDOG RD/WR ACCESS: IFG1 != 0x00 =====");
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`endif
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// WATCHDOG TEST: INTERVAL MODE /64
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// WATCHDOG TEST: INTERVAL MODE /64
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15==16'h2000);
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@(r15==16'h2000);
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if (r5 !== 16'h3401) tb_error("====== WATCHDOG INTERVAL MODE /64: R5 != 0x3401 =====");
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if (r5 !== 16'h3401) tb_error("====== WATCHDOG INTERVAL MODE /64: R5 != 0x3401 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64: R6 != 0x0000 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64: R6 != 0x0000 =====");
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if (r7 !== 16'h000D) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000D =====");
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`ifdef ASIC
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`ifdef WATCHDOG_MUX
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if (r7 !== 16'h000E) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000E (CONFIG 1) =====");
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`else
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`ifdef WATCHDOG_NOMUX_ACLK
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`ifdef ACLK_DIVIDER
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if (r7 !== 16'h019F) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x019F (CONFIG 1) =====");
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`else
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if (r7 !== 16'h0199) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x0199 (CONFIG 1) =====");
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`endif
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`else
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if (r7 !== 16'h000E) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000E (CONFIG 1) =====");
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`endif
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`endif
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`else
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if (r7 !== 16'h000D) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000D (CONFIG 1) =====");
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`endif
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@(r15==16'h2001);
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@(r15==16'h2001);
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if (r5 !== 16'h0002) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R5 != 0x0002 =====");
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if (r5 !== 16'h0002) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R5 != 0x0002 =====");
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if (r6 !== 16'h0001) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R6 != 0x0001 =====");
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if (r6 !== 16'h0001) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R6 != 0x0001 =====");
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if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R7 != 0x0000 =====");
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if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R7 != 0x0000 =====");
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if (r8 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R8 != 0x0000 =====");
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if (r8 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R8 != 0x0000 =====");
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`ifdef ASIC
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`ifdef WATCHDOG_MUX
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`else
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`ifdef WATCHDOG_NOMUX_ACLK
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// From there, force the watchdog clock to DCO_CLK to speedup simulation
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force lfxt_clk = dco_clk;
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`endif
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`endif
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`endif
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@(r15==16'h2002);
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@(r15==16'h2002);
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if (r5 !== 16'h0022) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R5 != 0x0022 =====");
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if (r5 !== 16'h0022) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R5 != 0x0022 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R6 != 0x0000 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R6 != 0x0000 =====");
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if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R7 != 0x0000 =====");
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if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R7 != 0x0000 =====");
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Line 89... |
Line 173... |
//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15==16'h3000);
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@(r15==16'h3000);
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if (r5 !== 16'h3403) tb_error("====== WATCHDOG INTERVAL MODE /512: R5 != 0x3403 =====");
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if (r5 !== 16'h3403) tb_error("====== WATCHDOG INTERVAL MODE /512: R5 != 0x3403 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /512: R6 != 0x0000 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /512: R6 != 0x0000 =====");
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if (r7 !== 16'h0067) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0067 =====");
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`ifdef ASIC
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if (r7 !== 16'h0068) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0068 =====");
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`else
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if (r7 !== 16'h0066) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0066 =====");
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`endif
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$display("Interval mode /512 mode test completed...");
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$display("Interval mode /512 mode test completed...");
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// WATCHDOG TEST: INTERVAL MODE /8192
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// WATCHDOG TEST: INTERVAL MODE /8192
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15==16'h4000);
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@(r15==16'h4000);
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if (r5 !== 16'h3404) tb_error("====== WATCHDOG INTERVAL MODE /8192: R5 != 0x3404 =====");
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if (r5 !== 16'h3404) tb_error("====== WATCHDOG INTERVAL MODE /8192: R5 != 0x3404 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /8192: R6 != 0x0000 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /8192: R6 != 0x0000 =====");
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`ifdef ASIC
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if (r7 !== 16'h0668) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0668 =====");
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`else
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if (r7 !== 16'h0667) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0667 =====");
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if (r7 !== 16'h0667) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0667 =====");
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`endif
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$display("Interval mode /8192 mode test completed...");
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$display("Interval mode /8192 mode test completed...");
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// WATCHDOG TEST: INTERVAL MODE /32768
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// WATCHDOG TEST: INTERVAL MODE /32768
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//--------------------------------------------------------
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//--------------------------------------------------------
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@(r15==16'h5000);
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@(r15==16'h5000);
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if (r5 !== 16'h3405) tb_error("====== WATCHDOG INTERVAL MODE /32768: R5 != 0x3405 =====");
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if (r5 !== 16'h3405) tb_error("====== WATCHDOG INTERVAL MODE /32768: R5 != 0x3405 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /32768: R6 != 0x0000 =====");
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if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /32768: R6 != 0x0000 =====");
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if (r7 !== 16'h199a) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199A =====");
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`ifdef ASIC
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if (r7 !== 16'h199B) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199B =====");
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`else
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if (r7 !== 16'h199A) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199A =====");
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`endif
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$display("Interval mode /32768 mode test completed...");
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$display("Interval mode /32768 mode test completed...");
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`else
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$display(" ===============================================");
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$display("| SIMULATION SKIPPED |");
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$display("| (the Watchdog is not included) |");
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$display(" ===============================================");
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$finish;
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`endif
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stimulus_done = 1;
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stimulus_done = 1;
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end
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end
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No newline at end of file
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No newline at end of file
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