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Line 28... |
/* */
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/* */
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/* Author(s): */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/* */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* $Rev: 18 $ */
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/* $Rev: 111 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */
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/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */
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/*===========================================================================*/
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/*===========================================================================*/
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.global main
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.global main
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.set DMEM_BASE, (__data_start )
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.set DMEM_200, (__data_start+0x00)
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.set DMEM_202, (__data_start+0x02)
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.set DMEM_204, (__data_start+0x04)
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.set DMEM_206, (__data_start+0x06)
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.set DMEM_208, (__data_start+0x08)
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.set DMEM_250, (__data_start+0x50)
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.set IE1, 0x0000
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.set IE1, 0x0000
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.set IFG1, 0x0002
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.set IFG1, 0x0002
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.set WDTCTL, 0x0120
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.set WDTCTL, 0x0120
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Line 56... |
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mov &IFG1, r4 ;# Check if we come out of a watchdog reset
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mov &IFG1, r4 ;# Check if we come out of a watchdog reset
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cmp #0x0000, r4
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cmp #0x0000, r4
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jeq RD_WR_ACCESS
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jeq RD_WR_ACCESS
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mov &0x0250, r15 ;# If yes, check RAM variable to see where to go next
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mov &DMEM_250, r15 ;# If yes, check RAM variable to see where to go next
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cmp #0x0000, r15
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cmp #0x0000, r15
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jeq RESET_64
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jeq RESET_64
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cmp #0x1000, r15
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cmp #0x1000, r15
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jeq RESET_512
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jeq RESET_512
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Line 74... |
jmp end_of_test
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jmp end_of_test
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/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */
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/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */
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RD_WR_ACCESS:
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RD_WR_ACCESS:
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mov #0x0000, &0x0250
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mov #0x0000, &DMEM_250
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mov &WDTCTL, &0x0200
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mov &WDTCTL, &DMEM_200
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mov #0x5aff, &WDTCTL
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mov #0x5aff, &WDTCTL
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mov &WDTCTL, &0x0202
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mov &WDTCTL, &DMEM_202
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mov #0x5a55, &WDTCTL
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mov #0x5a55, &WDTCTL
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mov &WDTCTL, &0x0204
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mov &WDTCTL, &DMEM_204
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mov #0x5aaa, &WDTCTL
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mov #0x5aaa, &WDTCTL
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mov &WDTCTL, &0x0206
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mov &WDTCTL, &DMEM_206
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mov #0x5a00, &WDTCTL
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mov #0x5a00, &WDTCTL
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mov &WDTCTL, &0x0208
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mov &WDTCTL, &DMEM_208
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mov #0xDEAD, &WDTCTL ;# Generate reset through wrong password
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mov #0xDEAD, &WDTCTL ;# Generate reset through wrong password
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: WATCHODG MODE /64 ------------ */
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/* -------------- WATCHDOG TEST: WATCHODG MODE /64 ------------ */
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RESET_64:
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RESET_64:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x1000, &0x0250
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mov #0x1000, &DMEM_250
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mov #0x5a0b, &WDTCTL ;# Enable watchdog mode /64 & clear counter
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mov #0x5a0b, &WDTCTL ;# Enable watchdog mode /64 & clear counter
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mov #0x0000, &0x0200
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mov #0x0000, &DMEM_200
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wait_loop_64:
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wait_loop_64:
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inc &0x0200
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inc &DMEM_200
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jmp wait_loop_64
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jmp wait_loop_64
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */
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RESET_512:
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RESET_512:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x2000, &0x0250
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mov #0x2000, &DMEM_250
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mov #0x5a0a, &WDTCTL ;# Enable watchdog mode /512 & clear counter
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mov #0x5a0a, &WDTCTL ;# Enable watchdog mode /512 & clear counter
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mov #0x0000, &0x0202
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mov #0x0000, &DMEM_202
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wait_loop_512:
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wait_loop_512:
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inc &0x0202
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inc &DMEM_202
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jmp wait_loop_512
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jmp wait_loop_512
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */
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RESET_8192:
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RESET_8192:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x3000, &0x0250
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mov #0x3000, &DMEM_250
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mov #0x5a09, &WDTCTL ;# Enable watchdog mode /8192 & clear counter
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mov #0x5a09, &WDTCTL ;# Enable watchdog mode /8192 & clear counter
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mov #0x0000, &0x0204
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mov #0x0000, &DMEM_204
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wait_loop_8192:
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wait_loop_8192:
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inc &0x0204
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inc &DMEM_204
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jmp wait_loop_8192
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jmp wait_loop_8192
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */
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/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */
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RESET_32768:
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RESET_32768:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x4000, &0x0250
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mov #0x4000, &DMEM_250
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mov #0x5a08, &WDTCTL ;# Enable interval mode /32768 & clear counter
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mov #0x5a08, &WDTCTL ;# Enable interval mode /32768 & clear counter
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mov #0x0000, &0x0206
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mov #0x0000, &DMEM_206
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wait_loop_32768:
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wait_loop_32768:
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inc &0x0206
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inc &DMEM_206
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jmp wait_loop_32768
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jmp wait_loop_32768
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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jmp end_of_test ;# Force end of test if watchdog reset don't happen
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CHECK_32768:
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CHECK_32768:
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bic.b #0x01, &IFG1
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bic.b #0x01, &IFG1
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mov #0x5000, &0x0250
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mov #0x5000, &DMEM_250
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/* ---------------------- END OF TEST --------------- */
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/* ---------------------- END OF TEST --------------- */
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end_of_test:
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end_of_test:
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nop
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nop
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