| Line 50... |
Line 50... |
{"Fusion" AFS1500 {Std -1 -2}}
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{"Fusion" AFS1500 {Std -1 -2}}
|
{"IGLOOE" AGLE600V5 {Std}}}
|
{"IGLOOE" AGLE600V5 {Std}}}
|
|
|
|
|
# Set the different RTL configurations to be analysed
|
# Set the different RTL configurations to be analysed
|
set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3}
|
set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER}
|
set rtlConfigs {{ 12 10 0 0 0 0 0 }
|
set rtlConfigs {{ 12 10 0 0 0 0 0 0}
|
{ 12 10 1 0 0 0 0 }
|
{ 12 10 1 0 0 0 0 0}
|
{ 12 10 1 1 0 0 0 }
|
{ 12 10 1 1 0 0 0 0}
|
{ 12 10 1 1 1 0 0 }
|
{ 12 10 1 1 1 0 0 0}
|
{ 12 10 1 1 1 1 0 }
|
{ 12 10 1 1 1 1 0 0}
|
{ 12 10 1 1 1 1 1 }}
|
{ 12 10 1 1 1 1 1 0}}
|
|
set rtlConfigs {{ 12 10 0 0 0 0 0 1}}
|
|
|
|
|
# RTL configuration files
|
# RTL configuration files
|
set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
|
set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
|
set designFiles {../../rtl/verilog/openMSP430.v
|
set designFiles {../../rtl/verilog/openMSP430.v
|
| Line 73... |
Line 74... |
../../rtl/verilog/omsp_sfr.v
|
../../rtl/verilog/omsp_sfr.v
|
../../rtl/verilog/omsp_watchdog.v
|
../../rtl/verilog/omsp_watchdog.v
|
../../rtl/verilog/omsp_dbg.v
|
../../rtl/verilog/omsp_dbg.v
|
../../rtl/verilog/omsp_dbg_uart.v
|
../../rtl/verilog/omsp_dbg_uart.v
|
../../rtl/verilog/omsp_dbg_hwbrk.v
|
../../rtl/verilog/omsp_dbg_hwbrk.v
|
|
../../rtl/verilog/omsp_multiplier.v
|
../../rtl/verilog/openMSP430_undefines.v
|
../../rtl/verilog/openMSP430_undefines.v
|
../../rtl/verilog/timescale.v
|
../../rtl/verilog/timescale.v
|
}
|
}
|
|
|
###############################################################################
|
###############################################################################
|
