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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [altera/] [run_analysis.tcl] - Diff between revs 63 and 68

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Rev 63 Rev 68
Line 49... Line 49...
                 {"Arria GX"       EP1AGX50CF484C {6}}
                 {"Arria GX"       EP1AGX50CF484C {6}}
                 {"Arria II GX"    EP2AGX45DF29C  {4 5 6}}
                 {"Arria II GX"    EP2AGX45DF29C  {4 5 6}}
                 {"Stratix"        EP1S10F484C    {5 6 7}}
                 {"Stratix"        EP1S10F484C    {5 6 7}}
                 {"Stratix II"     EP2S15F484C    {3 4 5}}
                 {"Stratix II"     EP2S15F484C    {3 4 5}}
                 {"Stratix III"    EP3SE50F484C   {2 3 4}}}
                 {"Stratix III"    EP3SE50F484C   {2 3 4}}}
set fpgaConfigs {{"Cyclone II"     EP2C20F484C    {7}}}
 
 
 
 
 
# Set the different RTL configurations to be analysed
# Set the different RTL configurations to be analysed
set rtlDefines  {PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3}
set rtlDefines  {PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER}
set rtlConfigs {{    12          10          0         0            0          0            0    }
set rtlConfigs {{    12          10          0         0            0          0            0         0}
                {    12          10          1         0            0          0            0    }
                {    12          10          1         0            0          0            0         0}
                {    12          10          1         1            0          0            0    }
                {    12          10          1         1            0          0            0         0}
                {    12          10          1         1            1          0            0    }
                {    12          10          1         1            1          0            0         0}
                {    12          10          1         1            1          1            0    }
                {    12          10          1         1            1          1            0         0}
                {    12          10          1         1            1          1            1    }}
                {    12          10          1         1            1          1            1         0}}
set rtlConfigs {{    12          10          0         0            0          0            0    }}
set rtlConfigs {{    12          10          0         0            0          0            0         1}}
 
 
 
 
# RTL configuration files
# RTL configuration files
set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
set rtlConfigFile  "./src/arch.v"
set rtlConfigFile  "./src/arch.v"

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