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Line 2... |
# #
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# #
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# CLOCK DEFINITION #
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# CLOCK DEFINITION #
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# #
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# #
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##############################################################################
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##############################################################################
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#set CLOCK_PERIOD 50.0; # 20 MHz
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#set CLOCK_PERIOD 40.0; # 25 MHz
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#set CLOCK_PERIOD 40.0; # 25 MHz
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#set CLOCK_PERIOD 30.0; # 33 MHz
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#set CLOCK_PERIOD 30.0; # 33 MHz
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#set CLOCK_PERIOD 25.0; # 40 MHz
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set CLOCK_PERIOD 20.0; # 50 MHz
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set CLOCK_PERIOD 20.0; # 50 MHz
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#set CLOCK_PERIOD 15.0; # 66 MHz
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#set CLOCK_PERIOD 15.0; # 66 MHz
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#set CLOCK_PERIOD 10.0; # 100 MHz
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#set CLOCK_PERIOD 10.0; # 100 MHz
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#set CLOCK_PERIOD 8.0; # 125 MHz
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#set CLOCK_PERIOD 8.0; # 125 MHz
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create_clock -name "clock" \
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create_clock -name "dco_clk" \
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-period "$CLOCK_PERIOD" \
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-period "$CLOCK_PERIOD" \
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-waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \
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-waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \
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[get_ports clock]
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[get_ports dco_clk]
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##############################################################################
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##############################################################################
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# #
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# #
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# CREATE PATH GROUPS #
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# CREATE PATH GROUPS #
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# #
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# #
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##############################################################################
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##############################################################################
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group_path -name REGOUT -to [all_outputs]
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group_path -name REGOUT -to [all_outputs]
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group_path -name REGIN -from [remove_from_collection [all_inputs] [get_ports clock]]
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group_path -name REGIN -from [remove_from_collection [all_inputs] [get_ports dco_clk]]
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group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports clock]] -to [all_outputs]
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group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports dco_clk]] -to [all_outputs]
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##############################################################################
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##############################################################################
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# #
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# #
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# BOUNDARY TIMINGS #
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# BOUNDARY TIMINGS #
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# #
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# #
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##############################################################################
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##############################################################################
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# NOTE: There are some path through between RAM and ROM signals.
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# NOTE: There are some path through between Program/Data memory signals
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# If required you might want to relax the constrains a bit.
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# which are limiting the maximum frequency achievable by the core.
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# The memory constraints set on these interfaces are therefore quite
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# critical regarding the achievable performance of the core.
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# As a consequence, the constrains on the pmem_*/dmem_* signals must
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# be set with some absolute values as they are specified by the targeted
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# process RAM/ROM generator.
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#===============#
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#================#
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# INPUT PORTS #
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# PROGRAM MEMORY #
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#===============#
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#================#
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set IRQ_DLY [expr ($CLOCK_PERIOD/100) * 30]
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set PMEM_DOUT_DLY 2.25
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set NMI_DLY [expr ($CLOCK_PERIOD/100) * 10]
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set PER_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set PMEM_ADDR_DLY 0.64
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set RAM_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set PMEM_CEN_DLY 0.63
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set ROM_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set PMEM_DIN_DLY 0.39
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set PMEM_WEN_DLY 0.44
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set RESET_N_DLY [expr ($CLOCK_PERIOD/100) * 75]
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set_input_delay $PMEM_DOUT_DLY -max -clock "dco_clk" [get_ports pmem_dout]
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set_input_delay 0 -min -clock "dco_clk" [get_ports pmem_dout]
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set_output_delay $PMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_addr]
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set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_addr]
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set_input_delay $IRQ_DLY -max -clock "clock" [get_ports irq]
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set_output_delay $PMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_cen]
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set_input_delay 0 -min -clock "clock" [get_ports irq]
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set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_cen]
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set_input_delay $NMI_DLY -max -clock "clock" [get_ports nmi]
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set_output_delay $PMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_din]
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set_input_delay 0 -min -clock "clock" [get_ports nmi]
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set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_din]
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set_input_delay $PER_DOUT_DLY -max -clock "clock" [get_ports per_dout]
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set_output_delay $PMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_wen]
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set_input_delay 0 -min -clock "clock" [get_ports per_dout]
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set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_wen]
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set_input_delay $RAM_DOUT_DLY -max -clock "clock" [get_ports ram_dout]
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set_input_delay 0 -min -clock "clock" [get_ports ram_dout]
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set_input_delay $ROM_DOUT_DLY -max -clock "clock" [get_ports rom_dout]
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#================#
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set_input_delay 0 -min -clock "clock" [get_ports rom_dout]
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# DATA MEMORY #
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#================#
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set_input_delay $RESET_N_DLY -max -clock "clock" -clock_fall [get_ports reset_n]
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set DMEM_DOUT_DLY 2.25
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set_input_delay 0 -min -clock "clock" -clock_fall [get_ports reset_n]
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set DMEM_ADDR_DLY 0.64
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set DMEM_CEN_DLY 0.63
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set DMEM_DIN_DLY 0.39
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set DMEM_WEN_DLY 0.44
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#===============#
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# OUTPUT PORTS #
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#===============#
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set PER_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set_input_delay $DMEM_DOUT_DLY -max -clock "dco_clk" [get_ports dmem_dout]
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set PER_DIN_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set_input_delay 0 -min -clock "dco_clk" [get_ports dmem_dout]
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set PER_WEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set PER_8B_CEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set_output_delay $DMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_addr]
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set PER_16B_CEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_addr]
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set RAM_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set_output_delay $DMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_cen]
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set RAM_CEN_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_cen]
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set RAM_DIN_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set RAM_WEN_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set ROM_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set_output_delay $DMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_din]
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set ROM_CEN_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_din]
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set MRST_DLY [expr ($CLOCK_PERIOD/100) * 75]
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set_output_delay $DMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_wen]
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set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_wen]
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set_output_delay $PER_ADDR_DLY -add_delay -max -clock "clock" [get_ports per_addr]
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#==========================#
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set_output_delay 0 -min -clock "clock" [get_ports per_addr]
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# REMAINING INPUT PORTS #
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#==========================#
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set_output_delay $PER_DIN_DLY -add_delay -max -clock "clock" [get_ports per_din]
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set IRQ_DLY [expr ($CLOCK_PERIOD/100) * 30]
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set_output_delay 0 -min -clock "clock" [get_ports per_din]
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set PER_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]
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set_output_delay $PER_WEN_DLY -add_delay -max -clock "clock" [get_ports per_wen]
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set_output_delay 0 -min -clock "clock" [get_ports per_wen]
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set_output_delay $PER_8B_CEN_DLY -add_delay -max -clock "clock" [get_ports per_8b_cen]
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set_input_delay $IRQ_DLY -max -clock "dco_clk" [get_ports irq]
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set_output_delay 0 -min -clock "clock" [get_ports per_8b_cen]
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set_input_delay 0 -min -clock "dco_clk" [get_ports irq]
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set_output_delay $PER_16B_CEN_DLY -add_delay -max -clock "clock" [get_ports per_16b_cen]
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set_input_delay $PER_DOUT_DLY -max -clock "dco_clk" [get_ports per_dout]
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set_output_delay 0 -min -clock "clock" [get_ports per_16b_cen]
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set_input_delay 0 -min -clock "dco_clk" [get_ports per_dout]
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set_output_delay $RAM_ADDR_DLY -add_delay -max -clock "clock" [get_ports ram_addr]
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set_output_delay 0 -min -clock "clock" [get_ports ram_addr]
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set_output_delay $RAM_CEN_DLY -add_delay -max -clock "clock" [get_ports ram_cen]
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#=========================#
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set_output_delay 0 -min -clock "clock" [get_ports ram_cen]
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# REMAINING OUTPUT PORTS #
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#=========================#
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set_output_delay $RAM_DIN_DLY -add_delay -max -clock "clock" [get_ports ram_din]
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set ACLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]
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set_output_delay 0 -min -clock "clock" [get_ports ram_din]
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set SMCLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]
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set DBG_FREEZE_DLY [expr ($CLOCK_PERIOD/100) * 85]
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set IRQ_ACC_DLY [expr ($CLOCK_PERIOD/100) * 60]
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set_output_delay $RAM_WEN_DLY -add_delay -max -clock "clock" [get_ports ram_wen]
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set PER_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set_output_delay 0 -min -clock "clock" [get_ports ram_wen]
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set PER_DIN_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set PER_WEN_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set PER_EN_DLY [expr ($CLOCK_PERIOD/100) * 25]
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set_output_delay $ROM_ADDR_DLY -add_delay -max -clock "clock" [get_ports rom_addr]
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set PUC_DLY [expr ($CLOCK_PERIOD/100) * 75]
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set_output_delay 0 -min -clock "clock" [get_ports rom_addr]
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set_output_delay $ROM_CEN_DLY -add_delay -max -clock "clock" [get_ports rom_cen]
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set_output_delay 0 -min -clock "clock" [get_ports rom_cen]
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set_output_delay $MRST_DLY -add_delay -max -clock "clock" -clock_fall [get_ports mrst]
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set_output_delay $ACLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports aclk_en]
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set_output_delay 0 -min -clock "clock" -clock_fall [get_ports mrst]
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set_output_delay 0 -min -clock "dco_clk" [get_ports aclk_en]
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set_output_delay $SMCLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports smclk_en]
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set_output_delay 0 -min -clock "dco_clk" [get_ports smclk_en]
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set_output_delay $DBG_FREEZE_DLY -add_delay -max -clock "dco_clk" [get_ports dbg_freeze]
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set_output_delay 0 -min -clock "dco_clk" [get_ports dbg_freeze]
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set_output_delay $IRQ_ACC_DLY -add_delay -max -clock "dco_clk" [get_ports irq_acc]
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set_output_delay 0 -min -clock "dco_clk" [get_ports irq_acc]
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set_output_delay $PER_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports per_addr]
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set_output_delay 0 -min -clock "dco_clk" [get_ports per_addr]
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set_output_delay $PER_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports per_din]
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set_output_delay 0 -min -clock "dco_clk" [get_ports per_din]
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set_output_delay $PER_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports per_wen]
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set_output_delay 0 -min -clock "dco_clk" [get_ports per_wen]
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set_output_delay $PER_EN_DLY -add_delay -max -clock "dco_clk" [get_ports per_en]
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set_output_delay 0 -min -clock "dco_clk" [get_ports per_en]
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set_output_delay $PUC_DLY -add_delay -max -clock "dco_clk" -clock_fall [get_ports puc]
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set_output_delay 0 -min -clock "dco_clk" -clock_fall [get_ports puc]
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#========================#
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#========================#
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# FEEDTHROUGH EXCEPTIONS #
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# FEEDTHROUGH EXCEPTIONS #
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#========================#
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#========================#
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#set_max_delay [expr 2.0 + $RAM_DOUT_DLY + $RAM_ADDR_DLY] \
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#set_max_delay [expr 2.0 + $DMEM_DOUT_DLY + $DMEM_ADDR_DLY] \
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# -from [get_ports ram_dout] \
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# -from [get_ports dmem_dout] \
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# -to [get_ports ram_addr] \
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# -to [get_ports dmem_addr] \
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# -group_path FEEDTHROUGH
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# -group_path FEEDTHROUGH
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No newline at end of file
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No newline at end of file
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#===============#
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# FALSE PATHS #
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#===============#
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# The following signals are internaly synchronized to
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# the dco_clk domain and can be set as false path.
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set_false_path -from dbg_uart_rxd
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set_false_path -to dbg_uart_txd
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set_false_path -from nmi
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set_false_path -from lfxt_clk
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set_false_path -from reset_n
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No newline at end of file
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No newline at end of file
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