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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [synthesis/] [synopsys/] [read.tcl] - Diff between revs 111 and 134

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Rev 111 Rev 134
Line 3... Line 3...
#                               READ DESING RTL                              #
#                               READ DESING RTL                              #
#                                                                            #
#                                                                            #
##############################################################################
##############################################################################
 
 
set DESIGN_NAME      "openMSP430"
set DESIGN_NAME      "openMSP430"
set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430.v
set RTL_SOURCE_FILES {../../rtl/verilog/openMSP430_defines.v
 
                      ../../rtl/verilog/openMSP430.v
                      ../../rtl/verilog/omsp_frontend.v
                      ../../rtl/verilog/omsp_frontend.v
                      ../../rtl/verilog/omsp_execution_unit.v
                      ../../rtl/verilog/omsp_execution_unit.v
                      ../../rtl/verilog/omsp_register_file.v
                      ../../rtl/verilog/omsp_register_file.v
                      ../../rtl/verilog/omsp_alu.v
                      ../../rtl/verilog/omsp_alu.v
                      ../../rtl/verilog/omsp_sfr.v
                      ../../rtl/verilog/omsp_sfr.v
Line 16... Line 17...
                      ../../rtl/verilog/omsp_watchdog.v
                      ../../rtl/verilog/omsp_watchdog.v
                      ../../rtl/verilog/omsp_dbg.v
                      ../../rtl/verilog/omsp_dbg.v
                      ../../rtl/verilog/omsp_dbg_uart.v
                      ../../rtl/verilog/omsp_dbg_uart.v
                      ../../rtl/verilog/omsp_dbg_hwbrk.v
                      ../../rtl/verilog/omsp_dbg_hwbrk.v
                      ../../rtl/verilog/omsp_multiplier.v
                      ../../rtl/verilog/omsp_multiplier.v
 
                      ../../rtl/verilog/omsp_sync_reset.v
                      ../../rtl/verilog/omsp_sync_cell.v
                      ../../rtl/verilog/omsp_sync_cell.v
 
                      ../../rtl/verilog/omsp_scan_mux.v
 
                      ../../rtl/verilog/omsp_and_gate.v
 
                      ../../rtl/verilog/omsp_wakeup_cell.v
 
                      ../../rtl/verilog/omsp_clock_gate.v
 
                      ../../rtl/verilog/omsp_clock_mux.v
}
}
 
 
set_svf ./results/$DESIGN_NAME.svf
set_svf ./results/$DESIGN_NAME.svf
define_design_lib WORK -path ./WORK
define_design_lib WORK -path ./WORK
analyze -format verilog $RTL_SOURCE_FILES
analyze -format verilog $RTL_SOURCE_FILES

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