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#=============================================================================#
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#=============================================================================#
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# Configuration #
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#=============================================================================#
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# Enable/Disable DC_ULTRA option
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set WITH_DC_ULTRA 1
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# Enable/Disable DFT insertion
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set WITH_DFT 1
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#=============================================================================#
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# Read technology library #
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# Read technology library #
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#=============================================================================#
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#=============================================================================#
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source -echo -verbose ./library.tcl
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source -echo -verbose ./library.tcl
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#=============================================================================#
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#=============================================================================#
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# Prevent assignment statements in the Verilog netlist.
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# Prevent assignment statements in the Verilog netlist.
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set_fix_multiple_port_nets -all -buffer_constants
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set_fix_multiple_port_nets -all -buffer_constants
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# Configure & Synthesize
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# Configuration
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current_design $DESIGN_NAME
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current_design $DESIGN_NAME
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set_max_area 0.0
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set_max_area 0.0
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set_flatten false
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set_flatten false
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set_structure true -timing true -boolean false
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set_structure true -timing true -boolean false
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# Synthesis
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if {$WITH_DC_ULTRA} {
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if {$WITH_DFT} {
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compile_ultra -scan -area_high_effort_script -no_autoungroup -no_boundary_optimization
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} else {
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compile_ultra -area_high_effort_script -no_autoungroup -no_boundary_optimization
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}
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} else {
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if {$WITH_DFT} {
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compile -scan -map_effort high -area_effort high
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} else {
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compile -map_effort high -area_effort high
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compile -map_effort high -area_effort high
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#compile_ultra -area_high_effort_script
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}
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#compile_ultra -area_high_effort_script -no_autoungroup -no_boundary_optimization
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}
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#=============================================================================#
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# DFT Insertion #
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#=============================================================================#
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if {$WITH_DFT} {
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# DFT Signal Type Definitions
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set_dft_signal -view spec -type ScanEnable -port scan_enable -active_state 1
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set_dft_signal -view existing_dft -type ScanEnable -port scan_enable -active_state 1
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set_dft_signal -view spec -type Constant -port scan_mode -active_state 1
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set_dft_signal -view existing_dft -type Constant -port scan_mode -active_state 1
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set_dft_signal -view existing_dft -type ScanClock -port dco_clk -timing [list 45 55]
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set_dft_signal -view existing_dft -type ScanClock -port lfxt_clk -timing [list 45 55]
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set_dft_signal -view existing_dft -type Reset -port reset_n -active 0
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# DFT Configuration
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set_dft_insertion_configuration -preserve_design_name true
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set_scan_configuration -style multiplexed_flip_flop
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set_scan_configuration -clock_mixing mix_clocks
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set_scan_configuration -chain_count 3
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# DFT Test Protocol Creation
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create_test_protocol
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# DFT Design Rule Check
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redirect -tee -file ./results/report.dft_drc {dft_drc}
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redirect -file ./results/report.dft_drc_verbose {dft_drc -verbose}
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redirect -file ./results/report.dft_drc_coverage {dft_drc -coverage_estimate}
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redirect -file ./results/report.dft_scan_config {report_scan_configuration}
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redirect -file ./results/report.dft_insert_config {report_dft_insertion_configuration}
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# Preview DFT insertion
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redirect -tee -file ./results/report.dft_preview {preview_dft}
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redirect -file ./results/report.dft_preview_all {preview_dft -show all -test_points all}
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# DFT insertion
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insert_dft
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# DFT Incremental Compile
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if {$WITH_DC_ULTRA} {
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compile_ultra -scan -incremental
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} else {
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compile -scan -incremental
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}
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# DFT Coverage estimate
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redirect -file ./results/report.dft_drc_coverage {dft_drc -coverage_estimate}
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}
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#=============================================================================#
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#=============================================================================#
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# Reports generation #
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# Reports generation #
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#=============================================================================#
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#=============================================================================#
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redirect ./results/report.timing {check_timing}
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redirect -file ./results/report.timing {check_timing}
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redirect ./results/report.constraints {report_constraints -all_violators -verbose}
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redirect -file ./results/report.constraints {report_constraints -all_violators -verbose}
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redirect ./results/report.paths.max {report_timing -path end -delay max -max_paths 200 -nworst 2}
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redirect -file ./results/report.paths.max {report_timing -path end -delay max -max_paths 200 -nworst 2}
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redirect ./results/report.full_paths.max {report_timing -path full -delay max -max_paths 5 -nworst 2}
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redirect -file ./results/report.full_paths.max {report_timing -path full -delay max -max_paths 5 -nworst 2}
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redirect ./results/report.paths.min {report_timing -path end -delay min -max_paths 200 -nworst 2}
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redirect -file ./results/report.paths.min {report_timing -path end -delay min -max_paths 200 -nworst 2}
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redirect ./results/report.full_paths.min {report_timing -path full -delay min -max_paths 5 -nworst 2}
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redirect -file ./results/report.full_paths.min {report_timing -path full -delay min -max_paths 5 -nworst 2}
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redirect ./results/report.refs {report_reference}
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redirect -file ./results/report.refs {report_reference}
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redirect ./results/report.area {report_area}
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redirect -file ./results/report.area {report_area}
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# Add NAND2 size equivalent report to the area report file
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# Add NAND2 size equivalent report to the area report file
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if {[info exists NAND2_NAME]} {
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if {[info exists NAND2_NAME]} {
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set nand2_area [get_attribute [get_lib_cell $LIB_WC_NAME/$NAND2_NAME] area]
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set nand2_area [get_attribute [get_lib_cell $LIB_WC_NAME/$NAND2_NAME] area]
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redirect -variable area {report_area}
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redirect -variable area {report_area}
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set nand2_eq [expr $area/$nand2_area]
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set nand2_eq [expr $area/$nand2_area]
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set fp [open "./results/report.area" a]
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set fp [open "./results/report.area" a]
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puts $fp ""
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puts $fp ""
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puts $fp "NAND2 equivalent cell area: $nand2_eq"
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puts $fp "NAND2 equivalent cell area: $nand2_eq"
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close $fp
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close $fp
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puts ""
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puts " ======================================================="
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puts " | AREA SUMMARY "
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puts " |-------------------------------------------------------"
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puts " |"
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puts " | $NAND2_NAME cell gate area: $nand2_area"
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puts " |"
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puts " | Total Area : $area"
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puts " | NAND2 equivalent cell area: $nand2_eq"
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puts " |"
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puts " ======================================================="
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puts ""
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}
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}
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#=============================================================================#
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#=============================================================================#
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# Dump gate level netlist & final DDC file #
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# Dump gate level netlist, final DDC file and Test protocol #
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#=============================================================================#
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#=============================================================================#
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current_design $DESIGN_NAME
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current_design $DESIGN_NAME
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change_name -rules verilog -hierarchy
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write -hierarchy -format verilog -output "./results/$DESIGN_NAME.gate.v"
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write -hierarchy -format verilog -output "./results/$DESIGN_NAME.gate.v"
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write -hierarchy -format ddc -output "./results/$DESIGN_NAME.ddc"
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write -hierarchy -format ddc -output "./results/$DESIGN_NAME.ddc"
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if {$WITH_DFT} {
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write_test_protocol -output "./results/$DESIGN_NAME.spf"
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}
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quit
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quit
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No newline at end of file
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No newline at end of file
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