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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [openMSP430_fpga.prj] - Diff between revs 111 and 134

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Rev 111 Rev 134
Line 80... Line 80...
`include "../../../rtl/verilog/openMSP430.v"
`include "../../../rtl/verilog/openMSP430.v"
`include "../../../rtl/verilog/omsp_frontend.v"
`include "../../../rtl/verilog/omsp_frontend.v"
`include "../../../rtl/verilog/omsp_execution_unit.v"
`include "../../../rtl/verilog/omsp_execution_unit.v"
`include "../../../rtl/verilog/omsp_register_file.v"
`include "../../../rtl/verilog/omsp_register_file.v"
`include "../../../rtl/verilog/omsp_alu.v"
`include "../../../rtl/verilog/omsp_alu.v"
`include "../../../rtl/verilog/omsp_mem_backbone.v"
 
`include "../../../rtl/verilog/omsp_clock_module.v"
 
`include "../../../rtl/verilog/omsp_sfr.v"
`include "../../../rtl/verilog/omsp_sfr.v"
 
`include "../../../rtl/verilog/omsp_clock_module.v"
 
`include "../../../rtl/verilog/omsp_mem_backbone.v"
`include "../../../rtl/verilog/omsp_watchdog.v"
`include "../../../rtl/verilog/omsp_watchdog.v"
`include "../../../rtl/verilog/omsp_sync_cell.v"
`include "../../../rtl/verilog/omsp_sync_cell.v"
 
`include "../../../rtl/verilog/omsp_sync_reset.v"
 
 
`include "../src/openMSP430_defines.v"
`include "../src/openMSP430_defines.v"
`ifdef DBG_EN
`ifdef DBG_EN
   `include "../../../rtl/verilog/omsp_dbg.v"
   `include "../../../rtl/verilog/omsp_dbg.v"
   `include "../../../rtl/verilog/omsp_dbg_uart.v"
   `include "../../../rtl/verilog/omsp_dbg_uart.v"

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