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<span style="font-weight: bold; text-decoration: underline; color: red;">Notice:</span><span style="color: red;">
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<span style="font-weight: bold; text-decoration: underline; color: red;">Notice:</span><span style="color: red;">
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the results presented here might vary depending on the tool versions,
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the results presented here might vary depending on the tool versions,
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applied timing constraints and exact configuration of the openMSP430 core.
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applied timing constraints and exact configuration of the openMSP430 core.
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The FPGA results were obtained using the free tool versions provided by
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The FPGA results were obtained using the free tool versions provided by
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the vendors (i.e ISE 11.1, QuartusII 9.1 & Libero 8.5). The ASIC synthesis was
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the vendors (i.e ISE 11.1, QuartusII 9.1 & Libero 8.5). The ASIC synthesis was
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run with Synopsys Design Compiler 2007.12 (without dc_ultra or any special feature).</span>
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run with Synopsys Design Compiler 2007.12 (<b>without dc_ultra or any special feature</b>).</span>
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<h1>1. Overview</h1>
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<h1>1. Overview</h1>
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<a name="1.1 FPGAs"></a>
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<a name="1.1 FPGAs"></a>
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<h2>1.1 FPGAs</h2>
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<h2>1.1 FPGAs</h2>
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