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<html><head><title>openMSP430 Core</title></head><body>
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<head>
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<title>openMSP430 Core</title>
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</head>
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<body>
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<h3>Table of content</h3>
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<h3>Table of content</h3>
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<ul>
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<ul>
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<li><a href="#1. Introduction">1. Introduction</a></li>
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<li><a href="#1.%20Introduction">1. Introduction</a></li>
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<li><a href="#2. Design"> 2. Design</a>
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<li><a href="#2.%20Design"> 2. Design</a>
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<ul>
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<ul>
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<li><a href="#2.1 Core"> 2.1 Core</a>
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<li><a href="#2.1%20Core"> 2.1 Core</a>
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<ul>
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<ul>
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<li><a href="#2.1.1 Design structure"> 2.1.1 Design structure</a></li>
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<li><a href="#2.1.1%20Design%20structure"> 2.1.1 Design structure</a></li>
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<li><a href="#2.1.2 Limitations"> 2.1.2 Limitations</a></li>
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<li><a href="#2.1.2%20Limitations"> 2.1.2 Limitations</a></li>
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<li><a href="#2.1.3 Configuration"> 2.1.3 Configuration</a></li>
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<li><a href="#2.1.3%20Configuration"> 2.1.3 Configuration</a></li>
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<ul>
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<ul>
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<li><a href="#2.1.3.1 Basic System Configuration"> 2.1.3.1 Basic System Configuration</a></li>
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<li><a href="#2.1.3.1%20Basic%20System%20Configuration"> 2.1.3.1 Basic System Configuration</a></li>
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<li><a href="#2.1.3.2 Advanced System Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
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<li><a href="#2.1.3.2%20Advanced%20System%20Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
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<li><a href="#2.1.3.3 Expert System Configuration"> 2.1.3.3 Expert System Configuration</a></li>
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<li><a href="#2.1.3.3%20Expert%20System%20Configuration"> 2.1.3.3 Expert System Configuration</a></li>
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</ul>
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</ul>
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<li><a href="#2.1.4 Memory mapping"> 2.1.4 Memory mapping</a></li>
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<li><a href="#2.1.4%20Memory%20mapping"> 2.1.4 Memory mapping</a></li>
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<li><a href="#2.1.5 Pinout"> 2.1.5 Pinout</a></li>
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<li><a href="#2.1.5%20Pinout"> 2.1.5 Pinout</a></li>
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<li><a href="#2.1.6 Instruction Cycles and Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
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<li><a href="#2.1.6%20Instruction%20Cycles%20and%20Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
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<li><a href="#2.1.7 Serial Debug Interface"> 2.1.7 Serial Debug Interface</a></li>
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<li><a href="#2.1.7%20Serial%20Debug%20Interface"> 2.1.7 Serial Debug Interface</a></li>
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</ul>
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</ul>
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</li>
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</li>
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<li><a href="#2.2 Peripherals"> 2.2 Peripherals</a>
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<li><a href="#2.2_System_Peripherals"> 2.2 System Peripherals</a>
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<ul>
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<ul>
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<li><a href="#2.2.1 Basic Clock Module"> 2.2.1 Basic Clock Module</a></li>
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<li><a href="#2.2.2 Watchdog Timer"> 2.2.2 Watchdog Timer</a></li>
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<li><a href="#2.2.1%20Basic%20Clock%20Module"> 2.2.1 Basic Clock Module: FPGA</a></li>
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<li><a href="#2.2.3 Digital I/O"> 2.2.3 Digital I/O</a></li>
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<li><a href="#2.2.2_Basic_Clock_Module_ASIC"> 2.2.2 Basic Clock Module: ASIC</a></li>
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<li><a href="#2.2.4 Timer A"> 2.2.4 Timer A</a></li>
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<li><a href="#2.2.3_SFR">2.2.3 SFR</a><br>
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<li><a href="#2.2.5 16x16 Hardware Multiplier"> 2.2.5 16x16 Hardware Multiplier</a></li>
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</ul>
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</li>
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</li>
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<li><a href="#2.2.2%20Watchdog%20Timer"> 2.2.4 Watchdog Timer</a></li>
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<li><a href="core.html#2.2.5%2016x16%20Hardware%20Multiplier"> 2.2.5 16x16 Hardware Multiplier</a></li>
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</ul>
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</ul>
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</li>
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</li>
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<li><a href="#2.3_Peripherals"> 2.3 External Peripherals</a></li>
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<ul>
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<li><a href="core.html#2.2.3%20Digital%20I/O">2.3.1 Digital I/O (FPGA ONLY)</a></li>
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<li><a href="core.html#2.2.4%20Timer%20A"> 2.3.2 Timer A (FPGA ONLY)</a></li>
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</ul>
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</ul></li>
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</ul>
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</ul>
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<a name="1. Introduction"></a>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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<h1>1. Introduction</h1>
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The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b> (note that the extended version of the architecture, the MSP430X, isn't supported by this IP). It is based on a Von Neumann architecture, with a single address space for instructions and data.
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The openMSP430 is a 16-bit microcontroller core compatible with <b><a href="http://www.ti.com/litv/pdf/slau049f">TI's MSP430 family</a></b>
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<br /><br />
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(note that the extended version of the architecture, the MSP430X, isn't
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This design has been implemented to be FPGA friendly. Therefore, the core doesn't contain any clock gate and has only a single clock domain. As a consequence, the clock management block has a few limitations.
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supported by this IP). It is based on a Von Neumann architecture, with
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<br /><br />
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a single address space for instructions and data.
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It is to be noted that this IP doesn't contain the instruction and data memory blocks internally (these are technology dependent hard macros which are connected to the IP during chip integration).
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<br><br>Depending on the selected configuration, this design can either be:<br>
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However the core is fully configurable in regard to the supported RAM and/or ROM sizes.
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<ul>
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<br /><br />
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<ul>
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In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
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<ul>
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<br /><br />
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<li> <span style="font-weight: bold;">FPGA friendly</span>: the core doesn't contain any clock gate and has only a single clock
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domain. As a consequence, in this mode, the <span style="font-style: italic;">Basic Clock Module</span> peripheral has a few
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limitations.<br>
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<br>
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</li>
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<li> <span style="font-weight: bold;">ASIC friendly</span>: the core contains up to all clock management
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options (clock muxes & low-power modes, fine grained clock
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gating, ...) and is also ready for scan insertion. In this mode, the <span style="font-style: italic;">Basic Clock Module</span> offers all features listed in the official <a href="http://www.ti.com/litv/pdf/slau049f">documentation</a>.<br>
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</li>
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</ul>
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</ul>
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</ul>
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<br>It is to be noted that this IP doesn't contain the instruction and
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data memory blocks internally (these are technology dependent hard
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macros which are connected to the IP during chip integration).
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However the core is fully configurable in regard to the supported RAM
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and/or ROM sizes.
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<br><br>In addition to the CPU core itself, several peripherals are
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also provided and can be easily connected to the core during
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integration.
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<br><br>
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<a name="2. Design"></a>
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<a name="2. Design"></a>
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<h1>2. Design</h1>
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<h1>2. Design</h1>
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<a name="2.1 Core"></a>
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<a name="2.1 Core"></a>
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<a name="2.1.1 Design structure"></a>
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<a name="2.1.1 Design structure"></a>
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<h3>2.1.1 Design structure</h3>
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<h3>2.1.1 Design structure</h3>
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The following diagram shows the openMSP430 design structure:
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The following diagram shows the openMSP430 design structure:
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<br /><br />
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<br><br>
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<img src="getimg.php?1267738921" width="100%" alt="CPU Structure" title="CPU Structure" />
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<img src="usercontent,img,1267738921" alt="CPU Structure" title="CPU Structure" width="80%">
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<br />
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<br>
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<ul>
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<ul>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Execution unit</b>: Containing the ALU and the register file, this module executes the current decoded instruction according to the execution state.</li>
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<li><b>Execution unit</b>:
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<li><b>Serial Debug Interface</b>: Contains all the required logic for a Nexus class 3 debugging unit (without trace). Communication with the host is done with a standard 8N1 serial interface.</li>
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Containing the ALU and the register file, this module executes the
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<li><b>Memory backbone</b>: This block performs a simple arbitration between the frontend and execution-unit for program, data and peripheral memory access.</li>
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current decoded instruction according to the execution state.</li>
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<li><b>Basic Clock Module</b>: Generates the ACLK and SMCLK enable signals.</li>
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<li><b>Serial Debug Interface</b>:
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Contains all the required logic for a Nexus class 3 debugging unit
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(without trace). Communication with the host is done with a standard
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two-wire 8N1 serial interface.</li>
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<li><b>Memory backbone</b>: This block
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performs a simple arbitration between the frontend and execution-unit
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for program, data and peripheral memory access.</li>
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<li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>Watchdog</b>: Although it is a peripheral, the watchdog is permanently included in the core because of its tight links with the NMI interrupts and the PUC reset generation.</li>
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<li><b>Watchdog</b>:
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<li><b>16x16 Multiplier</b>: The hardware multiplier peripheral is transparently supported by the GCC compiler and is also located in the core. It can be included or excluded at will through a Verilog define.</li>
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Although it is a peripheral, the watchdog is directly included in
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the core because of its tight links with the NMI interrupts and PUC
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reset generation.</li>
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<li><b>16x16 Multiplier</b>: The hardware
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multiplier peripheral is transparently supported by the GCC compiler
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and is therefore located in the core. It can be included or excluded at will
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through a Verilog define.</li>
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</ul>
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</ul>
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<a name="2.1.2 Limitations"></a>
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<a name="2.1.2 Limitations"></a>
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<h3>2.1.2 Limitations</h3>
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<h3>2.1.2 Limitations</h3>
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The known core limitations are the following:
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The known core limitations are the following:
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<br />
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<br>
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<ul>
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<ul>
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<li>Instructions can't be executed from the data memory.</li>
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<li>Instructions can't be executed from the data memory.</li>
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<li>SCG0 is not implemented (turns off DCO).</li>
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<li>MCLK can't be divided and can only have DCO_CLK as source (see <a href="#2.2.1 Basic Clock Module">Basic Clock Module</a> section).</li>
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</ul>
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</ul>
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<a name="2.1.3 Configuration"></a>
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<a name="2.1.3 Configuration"></a>
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<h3>2.1.3 Configuration</h3>
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<h3>2.1.3 Configuration</h3>
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It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br />
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It is possible to configure the openMSP430 core through the <b><i>openMSP430_defines.v</i></b> file located in the <b><i>rtl</i></b> directory (see <a href="http://www.opencores.org/project,openmsp430,file%20and%20directory%20description">file and directory description</a>).<br>In
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Three sets of parameters can be adjusted by the user in order to fully customize the core.
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this section, three sets of adjustabe user parameters are discussed in
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order to customize the core. A fourth set is available for ASIC
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<a name="2.1.3.1 Basic System Configuration"></a>
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specific options and will be discussed in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
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section. <a name="2.1.3.1 Basic System Configuration"></a>
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<h4>2.1.3.1 Basic System Configuration</h4>
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<h4>2.1.3.1 Basic System Configuration</h4>
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The basic system can be adjusted with the following set of defines in order to match the target system requirements.
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The basic system can be adjusted with the following set of defines in order to match the target system requirements.
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<br /><br />
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<br><br>
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<table border="0" cellspacing="4" cellpadding="0">
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<table border="0" cellpadding="0" cellspacing="4">
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<tr>
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<tbody><tr>
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<td width="35"></td>
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<td width="35"><br>
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<td bgcolor="#d0d0d0" width="3"></td>
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</td>
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<td width="15"></td>
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<td bgcolor="#d0d0d0" width="3"><br>
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</td>
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<td width="15"><br>
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</td>
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<td>
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<td>
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<code>
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<code>
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//============================================================================
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//============================================================================<br>
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<br />//============================================================================
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//============================================================================<br>
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<br />// BASIC SYSTEM CONFIGURATION
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// BASIC SYSTEM CONFIGURATION<br>
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<br />//============================================================================
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//============================================================================<br>
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<br />//============================================================================
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//============================================================================<br>
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<br />//
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//<br>
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<br />// Note: the sum of program, data and peripheral memory spaces must not
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// Note: the sum of program, data and peripheral memory spaces must not<br>
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<br />// exceed 64 kB
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// exceed 64 kB<br>
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<br />//
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//<br>
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<br />
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<br>
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<br />// Program Memory Size:
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// Program Memory Size:<br>
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<br />// Uncomment the required memory size
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//
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<br />//-------------------------------------------------------
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Uncomment the required memory size<br>
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<br />//`define PMEM_SIZE_59_KB
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//-------------------------------------------------------<br>
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<br />//`define PMEM_SIZE_55_KB
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//`define PMEM_SIZE_59_KB<br>
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<br />//`define PMEM_SIZE_54_KB
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//`define PMEM_SIZE_55_KB<br>
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<br />//`define PMEM_SIZE_51_KB
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//`define PMEM_SIZE_54_KB<br>
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<br />//`define PMEM_SIZE_48_KB
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//`define PMEM_SIZE_51_KB<br>
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<br />//`define PMEM_SIZE_41_KB
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//`define PMEM_SIZE_48_KB<br>
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<br />//`define PMEM_SIZE_32_KB
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//`define PMEM_SIZE_41_KB<br>
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<br />//`define PMEM_SIZE_24_KB
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//`define PMEM_SIZE_32_KB<br>
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<br />//`define PMEM_SIZE_16_KB
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//`define PMEM_SIZE_24_KB<br>
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<br />//`define PMEM_SIZE_12_KB
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//`define PMEM_SIZE_16_KB<br>
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<br />//`define PMEM_SIZE_8_KB
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//`define PMEM_SIZE_12_KB<br>
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<br />//`define PMEM_SIZE_4_KB
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//`define PMEM_SIZE_8_KB<br>
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<br />`define PMEM_SIZE_2_KB
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//`define PMEM_SIZE_4_KB<br>
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<br />//`define PMEM_SIZE_1_KB
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`define PMEM_SIZE_2_KB<br>
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<br />
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//`define PMEM_SIZE_1_KB<br>
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<br />// Data Memory Size:
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<br>
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<br />// Uncomment the required memory size
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<br>
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<br />//-------------------------------------------------------
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// Data Memory Size:<br>
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<br />//`define DMEM_SIZE_32_KB
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//
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<br />//`define DMEM_SIZE_24_KB
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Uncomment the required memory size<br>
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<br />//`define DMEM_SIZE_16_KB
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//-------------------------------------------------------<br>
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<br />//`define DMEM_SIZE_10_KB
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//`define DMEM_SIZE_32_KB<br>
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<br />//`define DMEM_SIZE_8_KB
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//`define DMEM_SIZE_24_KB<br>
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<br />//`define DMEM_SIZE_5_KB
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//`define DMEM_SIZE_16_KB<br>
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<br />//`define DMEM_SIZE_4_KB
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//`define DMEM_SIZE_10_KB<br>
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<br />//`define DMEM_SIZE_2p5_KB
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//`define DMEM_SIZE_8_KB<br>
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<br />//`define DMEM_SIZE_2_KB
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//`define DMEM_SIZE_5_KB<br>
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<br />//`define DMEM_SIZE_1_KB
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//`define DMEM_SIZE_4_KB<br>
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<br />//`define DMEM_SIZE_512_B
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//`define DMEM_SIZE_2p5_KB<br>
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<br />//`define DMEM_SIZE_256_B
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//`define DMEM_SIZE_2_KB<br>
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<br />`define DMEM_SIZE_128_B
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//`define DMEM_SIZE_1_KB<br>
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<br />
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//`define DMEM_SIZE_512_B<br>
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<br />// Include/Exclude Hardware Multiplier
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//`define DMEM_SIZE_256_B<br>
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<br />`define MULTIPLIER
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`define DMEM_SIZE_128_B<br>
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<br />
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<br>
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<br />// Include/Exclude Serial Debug interface
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<br>
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<br />`define DBG_EN
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// Include/Exclude Hardware Multiplier<br>
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</code>
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`define MULTIPLIER<br>
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</td>
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<br>
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</tr>
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<br>
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</table>
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// Include/Exclude Serial Debug interface<br>
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<br /><br />
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`define DBG_EN<br>
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</code></td></tr></tbody></table><br><br>
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The only design considerations at this stage are:
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The only design considerations at this stage are:
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<ul>
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<ul>
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<li>Make sure that the program and data memories have the correct size :-P</li>
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<li>Make sure that the program and data memories have the correct size :-P</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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</ul>
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<br />
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<br>
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<a name="2.1.3.2 Advanced System Configuration"></a>
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<a name="2.1.3.2 Advanced System Configuration"></a>
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<h4>2.1.3.2 Advanced System Configuration</h4>
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<h4>2.1.3.2 Advanced System Configuration</h4>
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In this section, some additional features are available in order to match the needs of more experienced users.
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In this section, some additional features are available in order to match the needs of more experienced users.
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<br /><br />
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<br><br>
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<table border="0" cellspacing="4" cellpadding="0">
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<table border="0" cellpadding="0" cellspacing="4">
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<tr>
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<tbody><tr>
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<td width="35"></td>
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<td width="35"><br>
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<td bgcolor="#d0d0d0" width="3"></td>
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<td width="15"></td>
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<td>
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<code>
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//============================================================================
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<br />//============================================================================
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<br />// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
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<br />//============================================================================
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<br />//============================================================================
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<br />
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<br />//-------------------------------------------------------
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<br />// Peripheral Memory Space:
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<br />//-------------------------------------------------------
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<br />// The original MSP430 architecture map the peripherals
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<br />// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
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<br />// The following defines allow you to expand this space
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<br />// up to 32 kB (i.e. from 0x0000 to 0x7fff).
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<br />// As a consequence, the data memory mapping will be
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<br />// shifted up and a custom linker script will therefore
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<br />// be required by the GCC compiler.
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<br />//-------------------------------------------------------
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<br />//`define PER_SIZE_32_KB
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<br />//`define PER_SIZE_16_KB
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<br />//`define PER_SIZE_8_KB
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<br />//`define PER_SIZE_4_KB
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<br />//`define PER_SIZE_2_KB
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<br />//`define PER_SIZE_1_KB
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<br />`define PER_SIZE_512_B
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<br />
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<br />
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<br />//-------------------------------------------------------
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<br />// Defines the debugger CPU_CTL.RST_BRK_EN reset value
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<br />// (CPU break on PUC reset)
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<br />//-------------------------------------------------------
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<br />// When defined, the CPU will automatically break after
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<br />// a PUC occurrence by default. This is typically usefull
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<br />// when the program memory can only be initialized through
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<br />// the serial debug interface.
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<br />//-------------------------------------------------------
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<br />//`define DBG_RST_BRK_EN
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<br />
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<br />
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<br />//-------------------------------------------------------
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<br />// Custom user version number
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<br />//-------------------------------------------------------
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<br />// This 5 bit field can be freely used in order to allow
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<br />// custom identification of the system through the debug
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<br />// interface.
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<br />// (see CPU_ID.USER_VERSION field in the documentation)
|
|
<br />//-------------------------------------------------------
|
|
<br />`define USER_VERSION 5'b00000
|
|
<br />
|
|
</code>
|
|
</td>
|
</td>
|
</tr>
|
<td bgcolor="#d0d0d0" width="3"><br>
|
</table>
|
</td>
|
<br /><br />
|
<td width="15"><br>
|
|
</td>
|
|
<td><code>//============================================================================<br>
|
|
//============================================================================<br>
|
|
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)<br>
|
|
//============================================================================<br>
|
|
//============================================================================<br>
|
|
<br>
|
|
//-------------------------------------------------------<br>
|
|
// Custom user version number<br>
|
|
//-------------------------------------------------------<br>
|
|
// This 5 bit field can be freely used in order to allow<br>
|
|
// custom identification of the system through the debug<br>
|
|
// interface.<br>
|
|
// (see CPU_ID.USER_VERSION field in the documentation)<br>
|
|
//-------------------------------------------------------<br>
|
|
`define USER_VERSION 5'b00000<br>
|
|
<br>
|
|
<br>
|
|
//-------------------------------------------------------<br>
|
|
// Include/Exclude Watchdog timer<br>
|
|
//-------------------------------------------------------<br>
|
|
// When excluded, the following functionality will be<br>
|
|
// lost:<br>
|
|
// - Watchog (both interval and watchdog modes)<br>
|
|
// - NMI interrupt edge selection<br>
|
|
// - Possibility to generate a software PUC reset<br>
|
|
//-------------------------------------------------------<br>
|
|
`define WATCHDOG<br>
|
|
<br>
|
|
<br>
|
|
///-------------------------------------------------------<br>
|
|
// Include/Exclude Non-Maskable-Interrupt support<br>
|
|
//-------------------------------------------------------<br>
|
|
`define NMI<br>
|
|
<br>
|
|
<br>
|
|
//-------------------------------------------------------<br>
|
|
// Input synchronizers<br>
|
|
//-------------------------------------------------------<br>
|
|
// In some cases, the asynchronous input ports might<br>
|
|
// already be synchronized externally.<br>
|
|
// If an extensive CDC design review showed that this<br>
|
|
// is really the case, the individual synchronizers<br>
|
|
// can be disabled with the following defines.<br>
|
|
//<br>
|
|
// Notes:<br>
|
|
// - all three signals are all sampled in the MCLK domain<br>
|
|
//<br>
|
|
// - the dbg_en signal reset the debug interface<br>
|
|
// when 0. Therefore make sure it is glitch free.<br>
|
|
//<br>
|
|
//-------------------------------------------------------<br>
|
|
`define SYNC_NMI<br>
|
|
//`define SYNC_CPU_EN<br>
|
|
//`define SYNC_DBG_EN<br>
|
|
</code><code><br>
|
|
<br>
|
|
</code><code>//-------------------------------------------------------<br>
|
|
// Peripheral Memory Space:<br>
|
|
//-------------------------------------------------------<br>
|
|
// The original MSP430 architecture map the peripherals<br>
|
|
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).<br>
|
|
// The following defines allow you to expand this space<br>
|
|
// up to 32 kB (i.e. from 0x0000 to 0x7fff).<br>
|
|
// As a consequence, the data memory mapping will be<br>
|
|
// shifted up and a custom linker script will therefore<br>
|
|
// be required by the GCC compiler.<br>
|
|
//-------------------------------------------------------<br>
|
|
//`define PER_SIZE_32_KB<br>
|
|
//`define PER_SIZE_16_KB<br>
|
|
//`define PER_SIZE_8_KB<br>
|
|
//`define PER_SIZE_4_KB<br>
|
|
//`define PER_SIZE_2_KB<br>
|
|
//`define PER_SIZE_1_KB<br>
|
|
`define PER_SIZE_512_B<br>
|
|
<br>
|
|
<br></code><code>//-------------------------------------------------------<br>
|
|
// Defines the debugger CPU_CTL.RST_BRK_EN reset value<br>
|
|
// (CPU break on PUC reset)<br>
|
|
//-------------------------------------------------------<br>
|
|
// When defined, the CPU will automatically break after<br>
|
|
// a PUC occurrence by default. This is typically useful<br>
|
|
// when the program memory can only be initialized through<br>
|
|
// the serial debug interface.<br>
|
|
//-------------------------------------------------------<br>
|
|
`define DBG_RST_BRK_EN</code><br>
|
|
</td></tr></tbody></table><br><br>
|
Design consideration at this stage are:
|
Design consideration at this stage are:
|
<ul>
|
<ul>
|
<li>Setting a peripheral memory space to something else than 512B will shift the data memory mapping up, which in turn will require the use of a custom linker script. If you don't know what a linker script is and if you don't want to know what it is, you should probably not modify this section.</li>
|
<li>Setting a peripheral memory space to something else than 512B
|
|
will shift the data memory mapping up, which in turn will require the
|
|
use of a custom linker script. If you don't know what a linker script
|
|
is and if you don't want to know what it is, you should probably not
|
|
modify this section.</li>
|
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
|
<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
|
</ul>
|
</ul>
|
<br />
|
<br>
|
<a name="2.1.3.3 Expert System Configuration"></a>
|
<a name="2.1.3.3 Expert System Configuration"></a>
|
<h4>2.1.3.3 Expert System Configuration</h4>
|
<h4>2.1.3.3 Expert System Configuration</h4>
|
|
In this section, you will find configuration options which are
|
In this section, you will find configuration options which will be relevant for roughly 0.01% of the users (according to an highly reliable market analysis ;-) ).
|
relevant for roughly 0.1% of the users (according to a highly
|
<br /><br />
|
reliable market analysis ;-) ).
|
<table border="0" cellspacing="4" cellpadding="0">
|
<br><br>
|
<tr>
|
<table border="0" cellpadding="0" cellspacing="4">
|
<td width="35"></td>
|
<tbody><tr>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td width="35"><br>
|
<td width="15"></td>
|
|
<td>
|
|
<code>
|
|
//============================================================================
|
|
<br />//============================================================================
|
|
<br />// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
|
|
<br />//============================================================================
|
|
<br />//============================================================================
|
|
<br />//
|
|
<br />// IMPORTANT NOTE: Please update following configuration options ONLY if
|
|
<br />// you have a good reason to do so... and if you know what
|
|
<br />// you are doing :-P
|
|
<br />//
|
|
<br />//============================================================================
|
|
<br />
|
|
<br />//-------------------------------------------------------
|
|
<br />// Number of hardware breakpoint units (each unit contains
|
|
<br />// two hardware address breakpoints):
|
|
<br />// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
|
|
<br />// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
|
|
<br />// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
|
|
<br />// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
|
|
<br />//-------------------------------------------------------
|
|
<br />// Please keep in mind that hardware breakpoints only
|
|
<br />// make sense whenever the program memory is not an SRAM
|
|
<br />// (i.e. Flash/OTP/ROM/...) or when you are interested
|
|
<br />// in data breakpoints (btw. not supported by GDB).
|
|
<br />//-------------------------------------------------------
|
|
<br />//`define DBG_HWBRK_0
|
|
<br />//`define DBG_HWBRK_1
|
|
<br />//`define DBG_HWBRK_2
|
|
<br />//`define DBG_HWBRK_3
|
|
<br />
|
|
<br />//-------------------------------------------------------
|
|
<br />// Enable/Disable the hardware breakpoint RANGE mode
|
|
<br />//-------------------------------------------------------
|
|
<br />// When enabled this feature allows the hardware breakpoint
|
|
<br />// units to stop the cpu whenever an instruction or data
|
|
<br />// access lays within an address range.
|
|
<br />// Note that this feature is not supported by GDB.
|
|
<br />//-------------------------------------------------------
|
|
<br />//`define DBG_HWBRK_RANGE
|
|
<br />
|
|
<br />//-------------------------------------------------------
|
|
<br />// Input synchronizers
|
|
<br />//-------------------------------------------------------
|
|
<br />// In some cases, the asynchronous input ports might
|
|
<br />// already be synchronized externally.
|
|
<br />// If an extensive CDC design review showed that this
|
|
<br />// is really the case, the individual synchronizers
|
|
<br />// can be disabled with the following defines.
|
|
<br />//
|
|
<br />// Notes:
|
|
<br />// - the dbg_en signal will reset the debug interface
|
|
<br />// when 0. Therefore make sure it is glitch free.
|
|
<br />//
|
|
<br />// - the dbg_uart_rxd synchronizer must be set to 1
|
|
<br />// when its reset is active.
|
|
<br />//-------------------------------------------------------
|
|
<br />`define SYNC_CPU_EN
|
|
<br />`define SYNC_DBG_EN
|
|
<br />`define SYNC_DBG_UART_RXD
|
|
<br />`define SYNC_NMI
|
|
<br />
|
|
</code>
|
|
</td>
|
</td>
|
</tr>
|
<td bgcolor="#d0d0d0" width="3"><br>
|
</table>
|
</td>
|
<br /><br />
|
<td width="15"><br>
|
|
</td>
|
|
<td>
|
|
<code> //============================================================================<br>
|
|
//============================================================================<br>
|
|
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )<br>
|
|
//============================================================================<br>
|
|
//============================================================================<br>
|
|
//<br>
|
|
// IMPORTANT NOTE: Please update following configuration options ONLY if<br>
|
|
//
|
|
you have a good reason to do so... and if you know what<br>
|
|
// you are doing :-P<br>
|
|
//<br>
|
|
//============================================================================<br>
|
|
<br>
|
|
//-------------------------------------------------------<br>// Number of hardware breakpoint/watchpoint units<br>
|
|
// (each unit contains two hardware addresses available<br>
|
|
// for breakpoints or watchpoints):<br>
|
|
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0<br>
|
|
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1<br>
|
|
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2<br>
|
|
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3<br>
|
|
//-------------------------------------------------------<br>
|
|
// Please keep in mind that hardware breakpoints only<br>
|
|
// make sense whenever the program memory is not an SRAM<br>
|
|
// (i.e. Flash/OTP/ROM/...) or when you are interested<br>
|
|
// in data breakpoints.<br>
|
|
//-------------------------------------------------------<br>
|
|
//`define DBG_HWBRK_0<br>
|
|
//`define DBG_HWBRK_1<br>
|
|
//`define DBG_HWBRK_2<br>
|
|
//`define DBG_HWBRK_3<br>
|
|
<br>
|
|
<br>
|
|
//-------------------------------------------------------<br>
|
|
// Enable/Disable the hardware breakpoint RANGE mode<br>
|
|
//-------------------------------------------------------<br>
|
|
// When enabled this feature allows the hardware breakpoint<br>
|
|
// units to stop the cpu whenever an instruction or data<br>
|
|
// access lays within an address range.<br>
|
|
// Note that this feature is not supported by GDB.<br>
|
|
//-------------------------------------------------------<br>
|
|
//`define DBG_HWBRK_RANGE<br>
|
|
<br>
|
|
<br>
|
|
//-------------------------------------------------------<br>
|
|
// ASIC version<br>
|
|
//-------------------------------------------------------<br>
|
|
// When uncommented, this define will enable the<br>
|
|
// ASIC system configuration section (see below) and<br>
|
|
// will activate scan support for production test.<br>
|
|
//<br>
|
|
// WARNING: if you target an FPGA, leave this define<br>
|
|
// commented.<br>
|
|
//-------------------------------------------------------<br>
|
|
//`define ASIC<br></code></td></tr></tbody></table><br><br>
|
Design consideration at this stage are:
|
Design consideration at this stage are:
|
<ul>
|
<ul>
|
<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
|
<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
|
</ul>
|
</ul>
|
<br />
|
<br>
|
All remaining defines located in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
|
All remaining defines located after the ASIC section in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
|
<br /><br />
|
<br><br>
|
|
|
<a name="2.1.4 Memory mapping"></a>
|
<a name="2.1.4 Memory mapping"></a>
|
<h3>2.1.4 Memory mapping</h3>
|
<h3>2.1.4 Memory mapping</h3>
|
|
|
As discussed in the earlier section, the openMSP430 memory mapping is fully configurable.<br />
|
As discussed earlier, the openMSP430 memory mapping is fully configurable.<br>The
|
The basic system configuration section allows to adjust program and data memory sizes while keeping 100% compatibility with the pre-existing linker scripts provided by MSPGCC4 (or any other toolchain for that matter).<br />
|
basic system configuration section allows to adjust program and data
|
However, an increasing number of users saw the 512B space available for peripherals in the standard MSP430 architecture as a limitation. Therefore, the advanced system configuration section give the possibility to up-scale the reserved peripheral address space anywhere between 512B and 32kB. As a consequence, the data memory space will be shifted up, which means that the linker script of your favorite toolchain will have to be modified accordingly.<br />
|
memory sizes while keeping 100% compatibility with the pre-existing
|
The following schematic should hopefully summarize this:<br />
|
linker scripts provided by MSPGCC (or any other toolchain for that
|
<br /><br />
|
matter).<br>
|
<img src="usercontent,img,1306066277" width="100%" alt="Memory mapping" title="Memory mapping" />
|
However, an increasing number of users saw the 512B space available for
|
<br />
|
peripherals in the standard MSP430 architecture as a limitation.
|
|
Therefore, the advanced system configuration section gives the
|
|
possibility to up-scale the reserved peripheral address space anywhere
|
|
between 512B and 32kB. As a consequence, the data memory space will be
|
|
shifted up, which means that the linker script of your favorite
|
|
toolchain will have to be modified accordingly.<br>
|
|
The following schematic should hopefully illustrate this:<br>
|
|
<br><br>
|
|
<img src="usercontent,img,1306066277" alt="Memory mapping" title="Memory mapping" width="80%">
|
|
<br>
|
|
|
<br /><br />
|
<br><br>
|
<a name="2.1.5 Pinout"></a>
|
<a name="2.1.5 Pinout"></a>
|
<h3>2.1.5 Pinout</h3>
|
<h3>2.1.5 Pinout</h3>
|
|
|
The full pinout of the openMSP430 core is provided in the following table:
|
The full pinout of the openMSP430 core is provided in the following table:
|
<br /><br />
|
<br><br>
|
<table border="1">
|
<table border="1">
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td style="vertical-align: top; text-align: center;"><span style="font-weight: bold;">Clock</span><br style="font-weight: bold;">
|
|
<span style="font-weight: bold;">Domain</span><br>
|
|
</td>
|
|
<td align="center"><b>Description</b></td> </tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Clocks & Power-Managment</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> cpu_en </td>
|
<td> cpu_en </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Enable CPU code execution (asynchronous) - set to 1 if unused </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
|
<td> Enable CPU code execution (asynchronous and non-glitchy).<br>
|
|
Set to 1 if unused. </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dco_clk </td>
|
<td> dco_clk </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Fast oscillator (fast clock), CPU clock </td>
|
<td style="vertical-align: top; text-align: center;">-<br>
|
|
</td>
|
|
<td> Fast oscillator (fast clock) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> lfxt_clk </td>
|
<td style="vertical-align: top;"> lfxt_clk</td>
|
<td> Input </td>
|
<td style="vertical-align: top;">Input<br>
|
<td> 1 </td>
|
</td>
|
<td> Low frequency oscillator (typ. 32kHz) </td>
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
|
</td>
|
|
<td style="vertical-align: top;"> Low frequency oscillator (typ. 32kHz)<br>
|
|
Set to 0 if unused.<br>
|
|
</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> mclk </td>
|
<td style="vertical-align: top;"> mclk</td>
|
<td> Output </td>
|
<td style="vertical-align: top;">Output<br>
|
<td> 1 </td>
|
</td>
|
<td> Main system clock </td>
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
|
</td>
|
|
<td style="vertical-align: top;"> Main system clock</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> aclk_en </td>
|
<td style="vertical-align: top;"> aclk_en</td>
|
<td> Output </td>
|
<td style="vertical-align: top;">Output</td>
|
<td> 1 </td>
|
<td style="vertical-align: top;">1<br>
|
<td> ACLK enable </td>
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td style="vertical-align: top;">FPGA ONLY: ACLK enable</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> smclk_en </td>
|
<td style="vertical-align: top;">smclk_en</td>
|
<td> Output </td>
|
<td style="vertical-align: top;">Output</td>
|
<td> 1 </td>
|
<td style="vertical-align: top;">1<br>
|
<td> SMCLK enable </td>
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td style="vertical-align: top;">FPGA ONLY: SMCLK enable</td>
|
</tr>
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">dco_enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Output<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">dco_clk<br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: Fast oscillator enable<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">dco_wkup<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Output<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: Fast oscillator wakeup (asynchronous)<br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td style="vertical-align: top;">lfxt_enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Output<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">lfxt_clk<br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: Low frequency oscillator enable<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">lfxt_wkup<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Output<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: Low frequency oscillator wakeup (asynchronous)<br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td style="vertical-align: top;">aclk<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Output<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: ACLK<br>
|
|
</td>
|
|
</tr>
|
|
|
|
<tr>
|
|
<td style="vertical-align: top;">smclk<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Output<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">-<br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: SMCLK<br>
|
|
</td>
|
|
</tr>
|
|
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
|
<tr>
|
|
<td style="vertical-align: top;">wkup<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Input<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: System Wake-up (asynchronous and non-glitchy)<br>
|
|
Set to 0 if unused.<br>
|
|
</td>
|
|
</tr>
|
|
<tr> <td colspan="5" align="center"> <b><i>Resets</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> puc_rst </td>
|
<td> puc_rst </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Main system reset </td>
|
<td> Main system reset </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> reset_n </td>
|
<td> reset_n </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Reset Pin (active low, asynchronous) </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
</td>
|
|
<td> Reset Pin (active low, asynchronous and non-glitchy) </td>
|
</tr>
|
</tr>
|
|
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> pmem_addr </td>
|
<td> pmem_addr </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> `PMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b> </td>
|
<td><small> `PMEM_AWIDTH</small> <b><sup><font color="#ff0000">1</font></sup></b> </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Program Memory address </td>
|
<td> Program Memory address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_cen </td>
|
<td> pmem_cen </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Program Memory chip enable (low active) </td>
|
<td> Program Memory chip enable (low active) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_din </td>
|
<td> pmem_din </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
<td> Program Memory data input (optional <b><sup><font color="#FF0000">2</font></sup></b>)</td>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Program Memory data input (optional <b><sup><font color="#ff0000">2</font></sup></b>)</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_dout </td>
|
<td> pmem_dout </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Program Memory data output </td>
|
<td> Program Memory data output </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> pmem_wen </td>
|
<td> pmem_wen </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 2 </td>
|
<td> 2 </td>
|
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#FF0000">2</font></sup></b>) </td>
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
|
<td> Program Memory write byte enable (low active) (optional <b><sup><font color="#ff0000">2</font></sup></b>) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> dmem_addr </td>
|
<td> dmem_addr </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> `DMEM_AWIDTH <b><sup><font color="#FF0000">1</font></sup></b></td>
|
<td><small> `DMEM_AWIDTH</small> <b><sup><font color="#ff0000">1</font></sup></b></td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Data Memory address </td>
|
<td> Data Memory address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dmem_cen </td>
|
<td> dmem_cen </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Data Memory chip enable (low active) </td>
|
<td> Data Memory chip enable (low active) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dmem_din </td>
|
<td> dmem_din </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Data Memory data input </td>
|
<td> Data Memory data input </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dmem_dout </td>
|
<td> dmem_dout </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Data Memory data output </td>
|
<td> Data Memory data output </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dmem_wen </td>
|
<td> dmem_wen </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 2 </td>
|
<td> 2 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Data Memory write byte enable (low active) </td>
|
<td> Data Memory write byte enable (low active) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> per_addr </td>
|
<td> per_addr </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 14 </td>
|
<td> 14 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Peripheral address </td>
|
<td> Peripheral address </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> per_din </td>
|
<td> per_din </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Peripheral data input </td>
|
<td> Peripheral data input </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> per_dout </td>
|
<td> per_dout </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 16 </td>
|
<td> 16 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Peripheral data output </td>
|
<td> Peripheral data output </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> per_en </td>
|
<td> per_en </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Peripheral enable (high active) </td>
|
<td> Peripheral enable (high active) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> per_we </td>
|
<td> per_we </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 2 </td>
|
<td> 2 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Peripheral write enable (high active) </td>
|
<td> Peripheral write enable (high active) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> irq </td>
|
<td> irq </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 14 </td>
|
<td> 14 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Maskable interrupts (one-hot signal) </td>
|
<td> Maskable interrupts (one-hot signal) </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> nmi </td>
|
<td> nmi </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Non-maskable interrupt (asynchronous) </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
|
<td> Non-maskable interrupt (asynchronous and non-glitchy)<br>
|
|
Set to 0 if unused.<br>
|
|
</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> irq_acc </td>
|
<td> irq_acc </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 14 </td>
|
<td> 14 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Interrupt request accepted (one-hot signal) </td>
|
<td> Interrupt request accepted (one-hot signal) </td>
|
</tr>
|
</tr>
|
|
|
<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> dbg_en </td>
|
<td> dbg_en </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
<td> Debug interface enable (asynchronous) <b><sup><font color="#FF0000">3</font></sup></b> </td>
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
|
|
or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
|
|
<td> Debug interface enable (asynchronous) <b><sup><font color="#ff0000">3</font></sup></b> </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dbg_freeze </td>
|
<td> dbg_freeze </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Freeze peripherals </td>
|
<td> Freeze peripherals </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dbg_uart_txd </td>
|
<td> dbg_uart_txd </td>
|
<td> Output </td>
|
<td> Output </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;">mclk<br>
|
|
</td>
|
<td> Debug interface: UART TXD </td>
|
<td> Debug interface: UART TXD </td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> dbg_uart_rxd </td>
|
<td> dbg_uart_rxd </td>
|
<td> Input </td>
|
<td> Input </td>
|
<td> 1 </td>
|
<td> 1 </td>
|
|
<td style="vertical-align: top; text-align: center;"><async><br>
|
|
</td>
|
<td> Debug interface: UART RXD (asynchronous) </td>
|
<td> Debug interface: UART RXD (asynchronous) </td>
|
|
</tr><tr align="center">
|
|
<td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
|
</tr>
|
</tr>
|
</table>
|
<tr>
|
<br />
|
<td style="vertical-align: top;">scan_enable<br>
|
<b><sup><font color="#FF0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
|
</td>
|
<b><sup><font color="#FF0000">2</font></sup></b>: These two optional ports can be connected whenever the program memory is a RAM. This will allow the user to load a program through the serial debug interface and to use software breakpoints.<br />
|
<td style="vertical-align: top;">Input<br>
|
<b><sup><font color="#FF0000">3</font></sup></b>: When disabled, the debug interface is hold into reset. As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br />
|
</td>
|
<br />
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;">dco_clk<br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: Scan enable (active during scan shifting)<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">scan_mode<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Input<br>
|
|
</td>
|
|
<td style="vertical-align: top;">1<br>
|
|
</td>
|
|
<td style="vertical-align: top; text-align: center;"><stable><br>
|
|
</td>
|
|
<td style="vertical-align: top;">ASIC ONLY: Scan mode<br>
|
|
</td>
|
|
</tr>
|
|
|
|
</tbody></table>
|
|
<br>
|
|
<b><sup><font color="#ff0000">1</font></sup></b>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br>
|
|
<b><sup><font color="#ff0000">2</font></sup></b>: These two optional
|
|
ports can be connected whenever the program memory is a RAM. This will
|
|
allow the user to load a program through the serial debug interface and
|
|
to use software breakpoints.<br>
|
|
<b><sup><font color="#ff0000">3</font></sup></b>: When disabled, the debug interface is hold into reset (and clock gated in ASIC mode). As a consequence, the <b><i>dbg_en</i></b> port can be used to reset the debug interface without disrupting the CPU execution.<br>
|
|
<b><sup><font color="#ff0000">4</font></sup></b>: Clock domain is selectable through configuration in the "openMSP430_defines.v" file (see Advanced System Configuration).<br>
|
|
<br>
|
|
<span style="text-decoration: underline; font-weight: bold;">Note:</span> in the FPGA configuration, the <span style="font-style: italic;">ASIC ONLY</span> signals must be left unconnected (for the outputs) and tied low (for the inputs).<br>
|
|
|
<a name="2.1.6 Instruction Cycles and Lengths"></a>
|
<a name="2.1.6 Instruction Cycles and Lengths"></a>
|
<h3>2.1.6 Instruction Cycles and Lengths</h3>
|
<h3>2.1.6 Instruction Cycles and Lengths</h3>
|
|
|
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br /><br />
|
Please note that a detailed description of the instruction and addressing modes can be found in the <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a></b> (Chapter 3).<br><br>
|
The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used, not the instruction itself.<br />
|
The number of CPU clock cycles required for an instruction depends on
|
|
the instruction format and the addressing modes used, not the
|
|
instruction itself.<br>
|
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
|
In the following tables, the number of clock cycles refers to the main clock (<i>MCLK</i>).
|
Differences with the original MSP430 are highlighted in green (the original value being red).
|
Differences with the original MSP430 are highlighted in green (the original value being red).
|
<ul>
|
<ul>
|
<li><b>Interrupt and Reset Cycles</b></li>
|
<li><b>Interrupt and Reset Cycles</b></li>
|
</ul>
|
</ul>
|
<table border="1">
|
<table border="1">
|
<tr> <td align="center"><b>Action</b> </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
|
<tbody><tr> <td align="center"><b>Action</b> </td> <td align="center"><b>No. of Cycles</b></td> <td align="center"><b>Length of Instruction</b></td> </tr>
|
<tr> <td> Return from interrupt (RETI) </td> <td align="center"> 5 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td> Return from interrupt (RETI) </td> <td align="center"> 5 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td> Interrupt accepted </td> <td align="center"> 6 </td> <td align="center"> - </td> </tr>
|
<tr> <td> Interrupt accepted </td> <td align="center"> 6 </td> <td align="center"> - </td> </tr>
|
<tr> <td> WDT reset </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
<tr> <td> WDT reset </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
<tr> <td> Reset (!RST/NMI) </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
<tr> <td> Reset (!RST/NMI) </td> <td align="center"> 4 </td> <td align="center"> - </td> </tr>
|
</table>
|
</tbody></table>
|
|
|
<ul>
|
<ul>
|
<li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
|
<li><b>Format-II (Single Operand) Instruction Cycles and Lengths</b></li>
|
</ul>
|
</ul>
|
<table border="1">
|
<table border="1">
|
<tr> <td rowspan="2" align="center"><b>Addressing Mode</b> </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
<tbody><tr> <td rowspan="2" align="center"><b>Addressing Mode</b> </td> <td colspan="3" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
<tr> <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
|
<tr> <td><b>RRA, RRC, SWPB, SXT</b></td> <td><b>PUSH</b></td> <td><b>CALL</b></td> </tr>
|
|
|
<tr> <td align="center"> Rn </td> <td align="center"> 1 </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> Rn </td> <td align="center"> 1 </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> @Rn </td> <td align="center"> 3 </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> @Rn </td> <td align="center"> 3 </td> <td align="center"> 4 </td> <td align="center"> 4 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> @Rn+ </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> @Rn+ </td> <td align="center"> 3 </td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"><b><font color="green">4 </font><font color="red"> (5)</font></b></td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> #N </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> #N </td> <td align="center"> N/A </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> X(Rn) </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> X(Rn) </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 5 </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
</table>
|
</tbody></table>
|
|
|
<ul>
|
<ul>
|
<li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
|
<li><b>Format-III (Jump) Instruction Cycles and Lengths</b></li>
|
</ul>
|
</ul>
|
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
|
All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not.
|
|
|
<ul>
|
<ul>
|
<li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
|
<li><b>Format-I (Double Operand) Instruction Cycles and Lengths</b></li>
|
</ul>
|
</ul>
|
<table border="1">
|
<table border="1">
|
<tr> <td colspan="2" align="center"><b>Addressing Mode</b> </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
<tbody><tr> <td colspan="2" align="center"><b>Addressing Mode</b> </td> <td rowspan="2" align="center"><b>No. of Cycles</b></td> <td rowspan="2" align="center"><b>Length of Instruction</b></td> </tr>
|
<tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
|
<tr> <td align="center"><b>Src</b></td> <td align="center"><b>Dst</b></td> </tr>
|
|
|
<tr> <td rowspan="5" align="center"> Rn </td> <td align="center"> Rm </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td rowspan="5" align="center"> Rn </td> <td align="center"> Rm </td> <td align="center"> 1 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 4 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td rowspan="5" align="center"> @Rn </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td rowspan="5" align="center"> @Rn </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (2)</font></b></td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td rowspan="5" align="center"> @Rn+ </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td rowspan="5" align="center"> @Rn+ </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 1 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td rowspan="5" align="center"> #N </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td rowspan="5" align="center"> #N </td> <td align="center"> Rm </td> <td align="center"> 2 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 5 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td rowspan="5" align="center"> x(Rn) </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td rowspan="5" align="center"> EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td rowspan="5" align="center"> EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"><b><font color="green">3 </font><font color="red"> (4)</font></b></td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td rowspan="5" align="center"> &EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td rowspan="5" align="center"> &EDE </td> <td align="center"> Rm </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> PC </td> <td align="center"> 3 </td> <td align="center"> 2 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> x(Rm) </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
<tr> <td align="center"> &EDE </td> <td align="center"> 6 </td> <td align="center"> 3 </td> </tr>
|
</table>
|
</tbody></table>
|
|
|
<a name="2.1.7 Serial Debug Interface"></a>
|
<a name="2.1.7 Serial Debug Interface"></a>
|
<h3>2.1.7 Serial Debug Interface</h3>
|
<h3>2.1.7 Serial Debug Interface</h3>
|
|
|
All the details about the Serial Debug Interface are located <a href="http://www.opencores.org/project/openmsp430/serial%20debug%20interface">here</a>.
|
All the details about the Serial Debug Interface are located <a href="http://opencores.org/project,openmsp430,serial%20debug%20interface">here</a>.<br>
|
<a name="2.2 Peripherals"></a>
|
<br>
|
<h2>2.2 Peripherals</h2>
|
<a name="2.2_System_Peripherals"></a>
|
|
<h2>2.2 System Peripherals</h2>
|
In addition to the CPU core itself, several peripherals are also provided and can be easily connected to the core during integration.
|
In addition to the CPU core itself, several peripherals are also
|
|
provided and can be easily connected to the core during integration.
|
|
The followings are directly integrated within the core because of their
|
|
tight links with the CPU.<br>
|
|
It is to be noted that <span style="font-weight: bold;">ALL</span> system peripherals support both ASIC and FPGA versions.<br>
|
<a name="2.2.1 Basic Clock Module"></a>
|
<a name="2.2.1 Basic Clock Module"></a>
|
<h3>2.2.1 Basic Clock Module</h3>
|
<h3>2.2.1 Basic Clock Module: FPGA<br>
|
|
</h3>In order to make an FPGA
|
In order to make an FPGA implementation as simple as possible (ideally, a non-designer should be able to do it), clock gates are not used in the design and neither are clock muxes.
|
implementation as simple as possible (ideally, a non-professional designer should be
|
<br />
|
able to do it), clock gates are not used in this design configuration and neither are
|
|
clock muxes.
|
|
<br>
|
With these constrains, the Basic Clock Module is implemented as following:
|
With these constrains, the Basic Clock Module is implemented as following:
|
<br /><br />
|
<br><br>
|
<img src="getimg.php?1249244393" alt="Clock structure diagram" title="Clock structure diagram" />
|
<img src="usercontent,img,1319831724" alt="Clock structure diagram" title="Clock structure diagram" width="80%">
|
<br />
|
<br>
|
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the CPU state machines in an IDLE state while MCLK will still be running.
|
<b>Note</b>: CPUOFF doesn't switch MCLK off and will instead bring the
|
<br /><br />
|
CPU state machines in an IDLE state while MCLK will still be running.
|
|
<br><br>
|
|
|
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
|
In order to '<i>clock</i>' a register with ACLK or SMCLK, the following structure needs to be implemented:
|
<br /><br />
|
<br><br>
|
<img src="getimg.php?1246434793" alt="Clock implementation example" title="Clock implementation example" />
|
<img src="usercontent,img,1246434793" alt="Clock implementation example" title="Clock implementation example">
|
<br /><br />
|
<br><br>For example, the following Verilog code would implement a counter clocked with SMCLK:
|
The following Verilog code would implement a counter clocked with SMCLK:
|
<br>
|
<br />
|
<table border="0" cellpadding="0" cellspacing="4">
|
<table border="0" cellspacing="4" cellpadding="0">
|
<tbody><tr>
|
<tr>
|
<td width="35"><br>
|
<td width="35"></td>
|
</td>
|
<td bgcolor="#d0d0d0" width="3"></td>
|
<td bgcolor="#d0d0d0" width="3"><br>
|
<td width="15"></td>
|
</td>
|
|
<td width="15"><br>
|
|
</td>
|
<td>
|
<td>
|
<code>
|
<code>
|
reg [7:0] test_cnt;
|
reg [7:0] test_cnt;
|
<br />
|
<br>
|
<br />always @ (posedge mclk or posedge puc_rst)
|
<br>always @ (posedge mclk or posedge puc_rst)
|
<br /> if (puc_rst) test_cnt <= 8'h00;
|
<br> if (puc_rst) test_cnt <= 8'h00;
|
<br /> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
|
<br> else if (smclk_en) test_cnt <= test_cnt + 8'h01;
|
</code>
|
</code>
|
</td>
|
</td>
|
</tr>
|
</tr>
|
</table>
|
</tbody></table>
|
<br /><br />
|
<br><br>
|
<b>Register Description</b>
|
<b>Register Description</b>
|
<ul>
|
<ul>
|
<li>DCOCTL: Not implemented</li>
|
<li>DCOCTL: Not implemented</li>
|
<li>BCSCTL1:
|
<li>BCSCTL1:
|
<ul>
|
<ul>
|
| Line 685... |
Line 971... |
<ul>
|
<ul>
|
<li>BCSCTL2[7:4]: Unused</li>
|
<li>BCSCTL2[7:4]: Unused</li>
|
<li>BCSCTL2[3] : SELS</li>
|
<li>BCSCTL2[3] : SELS</li>
|
<li>BCSCTL2[2:1]: DIVSx</li>
|
<li>BCSCTL2[2:1]: DIVSx</li>
|
<li>BCSCTL2[0] : Unused</li>
|
<li>BCSCTL2[0] : Unused</li>
|
</ul>
|
</ul></li>
|
</li>
|
</ul><a name="2.2.2_Basic_Clock_Module_ASIC"></a>
|
</ul>
|
<h3>2.2.2 Basic Clock Module: ASIC<br>
|
|
</h3>
|
|
When targeting an ASIC, up to all clock management
|
|
options available in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 4) can be included:<br><br>
|
|
|
|
<img src="usercontent,img,1319832480" alt="Clock structure diagram" title="Clock structure diagram" width="80%"><br>
|
|
Additional info can be found in the <a href="http://opencores.org/project,openmsp430,asic%20implementation">ASIC implementation</a>
|
|
section.<br>
|
|
<br>
|
|
<a name="2.2.3_SFR"></a>
|
|
<h3>2.2.3 SFR</h3>Following the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a>, this peripheral implements flags and interrupt enable bits for the Watchdog Timer and NMI:<br>
|
|
<br>
|
|
<table border="1">
|
|
|
|
|
|
<tbody><tr align="center">
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
|
<td colspan="8" rowspan="1" style="vertical-align: top;"><small style="font-weight: bold;">Bit Fields</small><br>
|
|
</td>
|
|
|
|
</tr>
|
|
<tr align="center">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<td style="vertical-align: top;"><small>7<br>
|
|
</small></td>
|
|
<td style="vertical-align: top;"><small>6<br>
|
|
</small></td>
|
|
<td style="vertical-align: top;"><small>5<br>
|
|
</small></td>
|
|
<td style="vertical-align: top;"><small>4<br>
|
|
</small></td>
|
|
<td style="vertical-align: top;"><small>3<br>
|
|
</small></td>
|
|
<td style="vertical-align: top;"><small>2<br>
|
|
</small></td>
|
|
<td style="vertical-align: top;"><small>1<br>
|
|
</small></td>
|
|
<td style="vertical-align: top;"><small>0<br>
|
|
</small></td>
|
|
|
|
|
|
</tr>
|
|
<tr align="center">
|
|
<td>IE1<br>
|
|
</td>
|
|
<td><small>0x0000</small></td>
|
|
|
|
|
|
|
|
<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><small> Reserved <br>
|
|
</small></td>
|
|
|
|
|
|
<td style="vertical-align: top;">NMIIE <b><sup><font color="#ff0000">1</font></sup></b></td>
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;"><small> Reserved </small>
|
|
</td>
|
|
|
|
|
|
<td style="vertical-align: top;">WDTIE <b><sup><font color="#ff0000">2</font></sup></b></td>
|
|
|
|
</tr>
|
|
<tr align="center">
|
|
<td>IFG1<br>
|
|
</td>
|
|
<td><small>0x0002</small></td>
|
|
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small><br>
|
|
|
|
</td>
|
|
|
|
|
|
<td style="vertical-align: top;">NMIIFG <b><sup><font color="#ff0000">1</font></sup></b></td>
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;"><small>Reserved</small></td>
|
|
|
|
|
|
<td style="vertical-align: top;">WDTIFG <b><sup><font color="#ff0000">2</font></sup></b></td>
|
|
|
|
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
|
|
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
|
|
<br>
|
|
In addition, two 16-bit read-only registers have been added in order
|
|
to let the software know with which version of the openMSP430 it is
|
|
running:<br>
|
|
<br>
|
|
<table border="1">
|
|
|
|
<tbody><tr align="center">
|
|
<td rowspan="2"><b><small>Register Name</small></b></td>
|
|
<td rowspan="2"><b><small>Address</small></b></td>
|
|
<td colspan="16"><b><small>Bit Field</small></b></td>
|
|
</tr>
|
|
<tr align="center">
|
|
<td><small>15</small></td><td><small>14</small></td>
|
|
<td><small>13</small></td><td><small>12</small></td>
|
|
<td><small>11</small></td><td><small>10</small></td>
|
|
<td><small> 9</small></td><td><small> 8</small></td>
|
|
<td><small> 7</small></td><td><small> 6</small></td>
|
|
<td><small> 5</small></td><td><small> 4</small></td>
|
|
<td><small> 3</small></td><td><small> 2</small></td>
|
|
<td><small> 1</small></td><td><small> 0</small></td>
|
|
</tr>
|
|
<tr align="center">
|
|
<td><small>CPU_ID_LO</small></td>
|
|
<td><small>0x0004</small></td>
|
|
<td colspan="7"><font size="-5">PER_SPACE</font></td>
|
|
<td colspan="5"><font size="-5">USER_VERSION</font></td>
|
|
<td colspan="1"><font size="-5">ASIC</font></td>
|
|
<td colspan="3"><font size="-5">CPU_VERSION</font></td>
|
|
</tr>
|
|
<tr align="center">
|
|
<td><small>CPU_ID_HI</small></td>
|
|
<td><small>0x0006</small></td>
|
|
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
|
|
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
|
|
<td colspan="1"><font size="-5">MPY</font></td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
<table border="0">
|
|
|
|
<tbody><tr>
|
|
<td> </td><td valign="top"><li><b>CPU_VERSION</b></li></td>
|
|
<td>: Current CPU version<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>ASIC</b></li></td>
|
|
<td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
|
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>USER_VERSION</b></li></td>
|
|
<td>: Reflects the value defined in the <b style="font-style: italic;">openMSP430_defines.v</b> file.</td>
|
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>PER_SPACE</b></li></td>
|
|
<td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
|
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>MPY</b></li></td>
|
|
<td>: This bit is set if the hardware multiplier is included in the current implementation</td>
|
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
|
|
<td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
|
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
|
|
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span> and <span style="font-style: italic;">CPU_ID_HI</span> are identical to the Serial Debug Interface register counterparts.<br>
|
<a name="2.2.2 Watchdog Timer"></a>
|
<a name="2.2.2 Watchdog Timer"></a>
|
<h3>2.2.2 Watchdog Timer</h3>
|
<h3>2.2.4 Watchdog Timer</h3>
|
|
|
|
|
|
|
|
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.<br>
|
|
|
|
<br>
|
|
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the watchdog timer should be included or not:<br>
|
|
<br>
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 10) have been implemented.
|
<tbody><tr>
|
|
<td width="35"><br>
|
|
</td>
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
|
</td>
|
|
<td width="15"><br>
|
|
</td>
|
|
<td>
|
|
<code>//-------------------------------------------------------<br>
|
|
// Include/Exclude Watchdog timer<br>
|
|
//-------------------------------------------------------<br>
|
|
// When excluded, the following functionality will be<br>
|
|
// lost:<br>
|
|
// - Watchog (both interval and watchdog modes)<br>
|
|
// - NMI interrupt edge selection<br>
|
|
// - Possibility to generate a software PUC reset<br>
|
|
//-------------------------------------------------------<br>
|
|
`define WATCHDOG</code></td></tr></tbody>
|
|
</table>
|
|
<br>
|
|
<a name="2.2.5 16x16 Hardware Multiplier"></a>
|
|
<h3>2.2.5 16x16 Hardware Multiplier</h3>
|
|
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
|
|
<br><br>
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not:<br><br>
|
|
<table border="0" cellpadding="0" cellspacing="4">
|
|
<tbody><tr>
|
|
<td width="35"><br>
|
|
</td>
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
|
</td>
|
|
<td width="15"><br>
|
|
</td>
|
|
<td>
|
|
<code>
|
|
// Include/Exclude Hardware Multiplier
|
|
<br>`define MULTIPLIER
|
|
</code>
|
|
</td>
|
|
</tr>
|
|
</tbody></table>
|
|
<a name="2.3_Peripherals"></a>
|
|
<h2>2.3 External Peripherals</h2>
|
|
The external peripherals labeld with the "FPGA ONLY" tag do not contain
|
|
any clock gate nor clock muxes and are clocked with MCLK only. This
|
|
mean that they don't support any of the low power modes and therefore are most likely not suited for an ASIC implementation.<br>
|
|
<br>
|
<a name="2.2.3 Digital I/O"></a>
|
<a name="2.2.3 Digital I/O"></a>
|
<h3>2.2.3 Digital I/O</h3>
|
<h3>2.3.1 Digital I/O (FPGA ONLY)<br>
|
|
</h3>
|
|
|
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 9) have been implemented.
|
<br /><br />
|
<br>
|
|
<br>
|
|
|
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
|
The following Verilog parameters will enable or disable the corresponding ports in order to save area (i.e. FPGA utilization):
|
<br /><br />
|
<br>
|
<table border="0" cellspacing="4" cellpadding="0">
|
<br>
|
<tr>
|
|
<td width="35"></td>
|
<table border="0" cellpadding="0" cellspacing="4">
|
<td bgcolor="#d0d0d0" width="3"></td>
|
|
<td width="15"></td>
|
<tbody><tr>
|
|
<td width="35"><br>
|
|
</td>
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
|
</td>
|
|
<td width="15"><br>
|
|
</td>
|
<td>
|
<td>
|
<code>
|
<code>
|
parameter P1_EN = 1'b1; // Enable Port 1
|
parameter P1_EN = 1'b1; // Enable Port 1
|
<br />parameter P2_EN = 1'b1; // Enable Port 2
|
<br>parameter P2_EN = 1'b1; // Enable Port 2
|
<br />parameter P3_EN = 1'b0; // Enable Port 3
|
<br>parameter P3_EN = 1'b0; // Enable Port 3
|
<br />parameter P4_EN = 1'b0; // Enable Port 4
|
<br>parameter P4_EN = 1'b0; // Enable Port 4
|
<br />parameter P5_EN = 1'b0; // Enable Port 5
|
<br>parameter P5_EN = 1'b0; // Enable Port 5
|
<br />parameter P6_EN = 1'b0; // Enable Port 6
|
<br>parameter P6_EN = 1'b0; // Enable Port 6
|
</code>
|
</code>
|
</td>
|
</td>
|
</tr>
|
</tr>
|
|
</tbody>
|
</table>
|
</table>
|
<br />
|
|
|
<br>
|
|
|
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
|
They can be updated as following during the module instantiation (here port 1, 2 and 3 are enabled):
|
<br /><br />
|
<br>
|
<table border="0" cellspacing="4" cellpadding="0">
|
<br>
|
<tr>
|
|
<td width="35"></td>
|
<table border="0" cellpadding="0" cellspacing="4">
|
<td bgcolor="#d0d0d0" width="3"></td>
|
|
<td width="15"></td>
|
<tbody><tr>
|
|
<td width="35"><br>
|
|
</td>
|
|
<td bgcolor="#d0d0d0" width="3"><br>
|
|
</td>
|
|
<td width="15"><br>
|
|
</td>
|
<td>
|
<td>
|
<code>
|
<code>
|
gpio #(.P1_EN(1),
|
gpio #(.P1_EN(1),
|
<br /> .P2_EN(1),
|
<br> .P2_EN(1),
|
<br /> .P3_EN(1),
|
<br> .P3_EN(1),
|
<br /> .P4_EN(0),
|
<br> .P4_EN(0),
|
<br /> .P5_EN(0),
|
<br> .P5_EN(0),
|
<br /> .P6_EN(0)) gpio_0 (
|
<br> .P6_EN(0)) gpio_0 (
|
</code>
|
</code>
|
</td>
|
</td>
|
</tr>
|
</tr>
|
|
</tbody>
|
</table>
|
</table>
|
<br />
|
|
|
<br>
|
|
|
The full pinout of the GPIO module is provided in the following table:
|
The full pinout of the GPIO module is provided in the following table:
|
<br /><br />
|
<br>
|
|
<br>
|
|
|
<table border="1">
|
<table border="1">
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks & Resets</i></b> </td></tr>
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
<tr> <td> puc_rst </td> <td> Input </td> <td> 1 </td> <td> Main system reset </td> </tr>
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
<tr> <td> irq_port1 </td> <td> Output </td> <td> 1 </td> <td> Port 1 interrupt </td> </tr>
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
<tr> <td> irq_port2 </td> <td> Output </td> <td> 1 </td> <td> Port 2 interrupt </td> </tr>
|
| Line 785... |
Line 1316... |
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Port 6</i></b> </td></tr>
|
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
|
<tr> <td> p6_din </td> <td> Input </td> <td> 8 </td> <td> Port 6 data input </td> </tr>
|
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
|
<tr> <td> p6_dout </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output </td> </tr>
|
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
|
<tr> <td> p6_dout_en </td> <td> Output </td> <td> 8 </td> <td> Port 6 data output enable </td> </tr>
|
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
|
<tr> <td> p6_sel </td> <td> Output </td> <td> 8 </td> <td> Port 6 function select </td> </tr>
|
|
</tbody>
|
</table>
|
</table>
|
|
|
|
|
<a name="2.2.4 Timer A"></a>
|
<a name="2.2.4 Timer A"></a>
|
<h3>2.2.4 Timer A</h3>
|
<h3>2.3.2 Timer A (FPGA ONLY)</h3>
|
|
|
|
|
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 11) have been implemented.
|
<br /><br />
|
<br>
|
|
<br>
|
|
|
The full pinout of the Timer A module is provided in the following table:
|
The full pinout of the Timer A module is provided in the following table:
|
<br /><br />
|
<br>
|
|
<br>
|
|
|
<table border="1">
|
<table border="1">
|
<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
|
<tbody><tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
|
|
<tr> <td colspan="4" align="center"> <b><i>Clocks, Resets & Debug</i></b> </td></tr>
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> mclk </td> <td> Input </td> <td> 1 </td> <td> Main system clock </td> </tr>
|
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
|
<tr> <td> aclk_en </td> <td> Input </td> <td> 1 </td> <td> ACLK enable (from CPU) </td> </tr>
|
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
|
<tr> <td> smclk_en </td> <td> Input </td> <td> 1 </td> <td> SMCLK enable (from CPU) </td> </tr>
|
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
|
<tr> <td> inclk </td> <td> Input </td> <td> 1 </td> <td> INCLK external timer clock (SLOW) </td> </tr>
|
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
|
<tr> <td> taclk </td> <td> Input </td> <td> 1 </td> <td> TACLK external timer clock (SLOW) </td> </tr>
|
| Line 829... |
Line 1369... |
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
|
<tr> <td colspan="4" align="center"> <b><i>Capture/Compare Unit 2</i></b> </td></tr>
|
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
|
<tr> <td> ta_cci2a </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input A </td> </tr>
|
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
|
<tr> <td> ta_cci2b </td> <td> Input </td> <td> 1 </td> <td> Timer A capture 2 input B </td> </tr>
|
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
|
<tr> <td> ta_out2 </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 </td> </tr>
|
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
|
<tr> <td> ta_out2_en </td> <td> Output </td> <td> 1 </td> <td> Timer A output 2 enable </td> </tr>
|
|
</tbody>
|
</table>
|
</table>
|
<br />
|
|
<b>Note</b>: for the same reason as with the Basic Clock Module, the two additional clock inputs (TACLK and INCLK) are internally synchronized with the MCLK domain.
|
|
As a consequence, TACLK and INCLK should be at least 2 times slowlier than MCLK, and if these clock are used toghether with the Timer A output unit, some jitter might be observed on the generated output.
|
|
If this jitter is critical for the application, ACLK and INCLK should idealy be derivated from DCO_CLK.
|
|
<br /><br />
|
|
<a name="2.2.5 16x16 Hardware Multiplier"></a>
|
|
<h3>2.2.5 16x16 Hardware Multiplier</h3>
|
|
|
|
100% of the features advertised in the <a href="http://www.ti.com/litv/pdf/slau049f">MSP430x1xx Family User's Guide</a> (Chapter 7) have been implemented.
|
<br>
|
<br /><br />
|
|
The following parameter in the <i>openMSP430_defines.v</i> file controls if the hardware multiplier should be included or not.
|
<b>Note</b>: for the same reason as with the Basic Clock Module FPGA version, the
|
<br /><br />
|
two additional clock inputs (TACLK and INCLK) are internally
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synchronized with the MCLK domain.
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As a consequence, TACLK and INCLK should be at least 2 times slowlier
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<td width="35"></td>
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than MCLK, and if these clock are used toghether with the Timer A
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output unit, some jitter might be observed on the generated output.
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<td width="15"></td>
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If this jitter is critical for the application, ACLK and INCLK should
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<td>
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idealy be derivated from DCO_CLK.
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<code>
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<br>
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// Include/Exclude Hardware Multiplier
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<br>
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<br />`define MULTIPLIER
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<br>
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</code>
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</td>
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</tr>
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