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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
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<html><head><title>openMSP430 Core</title></head><body>
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<html><head><title>openMSP430 Core</title></head>
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<body>
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<h3>Table of content</h3>
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<h3>Table of content</h3>
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<ul>
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<ul>
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<li><a href="#1.%20Introduction">1. Introduction</a></li>
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<li><a href="#1.%20Introduction">1. Introduction</a></li>
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<li><a href="#2.%20Design"> 2. Design</a>
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<li><a href="#2.%20Design"> 2. Design</a>
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<ul>
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<ul>
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<li><a href="#2.1.3%20Configuration"> 2.1.3 Configuration</a></li>
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<li><a href="#2.1.3%20Configuration"> 2.1.3 Configuration</a></li>
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<ul>
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<ul>
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<li><a href="#2.1.3.1%20Basic%20System%20Configuration"> 2.1.3.1 Basic System Configuration</a></li>
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<li><a href="#2.1.3.1%20Basic%20System%20Configuration"> 2.1.3.1 Basic System Configuration</a></li>
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<li><a href="#2.1.3.2%20Advanced%20System%20Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
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<li><a href="#2.1.3.2%20Advanced%20System%20Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
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<li><a href="#2.1.3.3%20Expert%20System%20Configuration"> 2.1.3.3 Expert System Configuration</a></li>
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<li><a href="#2.1.3.3%20Expert%20System%20Configuration"> 2.1.3.3 Expert System Configuration</a></li>
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<li><a href="#2.1.3.4%20Parameters%20For%20Multi-Core%20Systems"> 2.1.3.4 Parameters For Multi-Core Systems</a></li>
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</ul>
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</ul>
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<li><a href="#2.1.4%20Memory%20mapping"> 2.1.4 Memory mapping</a></li>
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<li><a href="#2.1.4%20Memory%20mapping"> 2.1.4 Memory mapping</a></li>
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<li><a href="#2.1.5%20Pinout"> 2.1.5 Pinout</a></li>
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<li><a href="#2.1.5%20Pinout"> 2.1.5 Pinout</a></li>
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<li><a href="#2.1.6%20Instruction%20Cycles%20and%20Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
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<li><a href="#2.1.6%20Instruction%20Cycles%20and%20Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
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<li><a href="#2.1.7%20Serial%20Debug%20Interface"> 2.1.7 Serial Debug Interface</a></li>
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<li><a href="#2.1.7%20Serial%20Debug%20Interface"> 2.1.7 Serial Debug Interface</a></li>
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<li><a href="#2.1.8%20Benchmark%20results"> 2.1.8 Benchmark results</a></li>
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<ul>
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<li><a href="#2.1.8.1%20Dhrystone">2.1.8.1 Dhrystone</a></li>
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<li><a href="#2.1.8.2%20CoreMark">2.1.8.2 CoreMark</a></li>
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</ul>
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</ul>
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</ul>
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</li>
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</li>
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<li><a href="#2.2_System_Peripherals"> 2.2 System Peripherals</a>
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<li><a href="#2.2_System_Peripherals"> 2.2 System Peripherals</a>
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<ul>
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<ul>
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<a name="2.1.1 Design structure"></a>
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<a name="2.1.1 Design structure"></a>
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<h3>2.1.1 Design structure</h3>
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<h3>2.1.1 Design structure</h3>
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The following diagram shows the openMSP430 design structure:
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The following diagram shows the openMSP430 design structure:
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<br><br>
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<br><br>
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<img src="usercontent,img,1267738921" alt="CPU Structure" title="CPU Structure" width="80%">
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<img src="http://opencores.org/usercontent,img,1354053264" alt="CPU Structure" title="CPU Structure" width="80%">
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<br>
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<br>
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<ul>
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<ul>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Execution unit</b>:
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<li><b>Execution unit</b>:
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Containing the ALU and the register file, this module executes the
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Containing the ALU and the register file, this module executes the
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current decoded instruction according to the execution state.</li>
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current decoded instruction according to the execution state.</li>
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<li><b>Serial Debug Interface</b>:
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<li><b>Serial Debug Interface</b>:
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Contains all the required logic for a Nexus class 3 debugging unit
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Contains all the required logic for a Nexus class 3 debugging unit
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(without trace). Communication with the host is done with a standard
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(without trace). Communication with the host is performed with a standard
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two-wire 8N1 serial interface.</li>
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two-wire interface following either the UART 8N1 or I<sup>2</sup>C serial protocol.</li>
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<li><b>Memory backbone</b>: This block
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<li><b>Memory backbone</b>: This block
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performs a simple arbitration between the frontend and execution-unit
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performs a simple arbitration between the frontend and execution-unit
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for program, data and peripheral memory access.</li>
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for program, data and peripheral memory access.</li>
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<li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
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<li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<br>
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<br>
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// Program Memory Size:<br>
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// Program Memory Size:<br>
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//
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//
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Uncomment the required memory size<br>
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Uncomment the required memory size<br>
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//-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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//`define PMEM_SIZE_CUSTOM<br>
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//`define PMEM_SIZE_59_KB<br>
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//`define PMEM_SIZE_59_KB<br>
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//`define PMEM_SIZE_55_KB<br>
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//`define PMEM_SIZE_55_KB<br>
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//`define PMEM_SIZE_54_KB<br>
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//`define PMEM_SIZE_54_KB<br>
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//`define PMEM_SIZE_51_KB<br>
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//`define PMEM_SIZE_51_KB<br>
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//`define PMEM_SIZE_48_KB<br>
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//`define PMEM_SIZE_48_KB<br>
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<br>
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<br>
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// Data Memory Size:<br>
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// Data Memory Size:<br>
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//
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//
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Uncomment the required memory size<br>
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Uncomment the required memory size<br>
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//-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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//`define DMEM_SIZE_CUSTOM<br>
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//`define DMEM_SIZE_32_KB<br>
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//`define DMEM_SIZE_32_KB<br>
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//`define DMEM_SIZE_24_KB<br>
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//`define DMEM_SIZE_24_KB<br>
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//`define DMEM_SIZE_16_KB<br>
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//`define DMEM_SIZE_16_KB<br>
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//`define DMEM_SIZE_10_KB<br>
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//`define DMEM_SIZE_10_KB<br>
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//`define DMEM_SIZE_8_KB<br>
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//`define DMEM_SIZE_8_KB<br>
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<ul>
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<ul>
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<li>Make sure that the program and data memories have the correct size :-P</li>
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<li>Make sure that the program and data memories have the correct size :-P</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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</ul>
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<br>
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<br>
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<b><u>Note:</u></b> when selected, custom memory sizes can be specified in the "Expert System Configuration" section.
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<br>
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<br>
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<a name="2.1.3.2 Advanced System Configuration"></a>
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<a name="2.1.3.2 Advanced System Configuration"></a>
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<h4>2.1.3.2 Advanced System Configuration</h4>
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<h4>2.1.3.2 Advanced System Configuration</h4>
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In this section, some additional features are available in order to match the needs of more experienced users.
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In this section, some additional features are available in order to match the needs of more experienced users.
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// up to 32 kB (i.e. from 0x0000 to 0x7fff).<br>
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// up to 32 kB (i.e. from 0x0000 to 0x7fff).<br>
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// As a consequence, the data memory mapping will be<br>
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// As a consequence, the data memory mapping will be<br>
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// shifted up and a custom linker script will therefore<br>
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// shifted up and a custom linker script will therefore<br>
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// be required by the GCC compiler.<br>
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// be required by the GCC compiler.<br>
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//-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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//`define PER_SIZE_CUSTOM<br>
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//`define PER_SIZE_32_KB<br>
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//`define PER_SIZE_32_KB<br>
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//`define PER_SIZE_16_KB<br>
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//`define PER_SIZE_16_KB<br>
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//`define PER_SIZE_8_KB<br>
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//`define PER_SIZE_8_KB<br>
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//`define PER_SIZE_4_KB<br>
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//`define PER_SIZE_4_KB<br>
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//`define PER_SIZE_2_KB<br>
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//`define PER_SIZE_2_KB<br>
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is and if you don't want to know what it is, you should probably not
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is and if you don't want to know what it is, you should probably not
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modify this section.</li>
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modify this section.</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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<li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
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</ul>
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</ul>
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<br>
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<br>
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<b><u>Note:</u></b> when selected, custom peripheral memory space can be specified in the "Expert System Configuration" section.
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<br>
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<br>
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<a name="2.1.3.3 Expert System Configuration"></a>
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<a name="2.1.3.3 Expert System Configuration"></a>
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<h4>2.1.3.3 Expert System Configuration</h4>
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<h4>2.1.3.3 Expert System Configuration</h4>
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In this section, you will find configuration options which are
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In this section, you will find configuration options which are
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relevant for roughly 0.1% of the users (according to a highly
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relevant for roughly 0.1% of the users (according to a highly
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reliable market analysis ;-) ).
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reliable market analysis ;-) ).
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you have a good reason to do so... and if you know what<br>
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you have a good reason to do so... and if you know what<br>
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// you are doing :-P<br>
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// you are doing :-P<br>
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//<br>
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//<br>
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//============================================================================<br>
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//============================================================================<br>
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<br>
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<br>
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//-------------------------------------------------------<br>
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// Select serial debug interface protocol<br>
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//-------------------------------------------------------<br>
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// DBG_UART -> Enable UART (8N1) debug interface<br>
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// DBG_I2C -> Enable I2C debug interface<br>
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//-------------------------------------------------------<br>
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`define DBG_UART<br>
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//`define DBG_I2C<br>
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<br>
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<br>
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//-------------------------------------------------------<br>
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// Enable the I2C broadcast address<br>
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//-------------------------------------------------------<br>
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// For multicore systems, a common I2C broadcast address<br>
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// can be given to all oMSP cores in order to<br>
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// synchronously RESET, START, STOP, or STEP all CPUs<br>
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// at once with a single I2C command.<br>
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// If you have a single openMSP430 in your system,<br>
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// this option can stay commented-out.<br>
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//-------------------------------------------------------<br>
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//`define DBG_I2C_BROADCAST<br>
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<br>
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<br>
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//-------------------------------------------------------<br>// Number of hardware breakpoint/watchpoint units<br>
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//-------------------------------------------------------<br>// Number of hardware breakpoint/watchpoint units<br>
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// (each unit contains two hardware addresses available<br>
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// (each unit contains two hardware addresses available<br>
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// for breakpoints or watchpoints):<br>
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// for breakpoints or watchpoints):<br>
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// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0<br>
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// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0<br>
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1<br>
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1<br>
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//-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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//`define DBG_HWBRK_RANGE<br>
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//`define DBG_HWBRK_RANGE<br>
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<br>
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<br>
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<br>
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<br>
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//-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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// Custom Program/Data and Peripheral Memory Spaces<br>
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//-------------------------------------------------------<br>
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// The following values are valid only if the<br>
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// corresponding *_SIZE_CUSTOM defines are uncommented:<br>
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//<br>
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// - *_SIZE : size of the section in bytes.<br>
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// - *_AWIDTH : address port width, this value must allow<br>
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// to address all WORDS of the section<br>
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// (i.e. the *_SIZE divided by 2)<br>
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//-------------------------------------------------------<br>
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<br>
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// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)<br>
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`define PMEM_CUSTOM_AWIDTH 10<br>
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`define PMEM_CUSTOM_SIZE 2048<br>
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<br>
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// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)<br>
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`define DMEM_CUSTOM_AWIDTH 6<br>
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`define DMEM_CUSTOM_SIZE 128<br>
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<br>
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// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)<br>
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`define PER_CUSTOM_AWIDTH 8<br>
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`define PER_CUSTOM_SIZE 512<br>
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<br>
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<br>
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//-------------------------------------------------------<br>
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// ASIC version<br>
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// ASIC version<br>
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//-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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// When uncommented, this define will enable the<br>
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// When uncommented, this define will enable the<br>
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// ASIC system configuration section (see below) and<br>
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// ASIC system configuration section (see below) and<br>
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// will activate scan support for production test.<br>
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// will activate scan support for production test.<br>
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<ul>
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<ul>
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<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
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<li>This is the expert section... so you know what your are doing anyway right ;-)</li>
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</ul>
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</ul>
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<br>
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<br>
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All remaining defines located after the ASIC section in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
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All remaining defines located after the ASIC section in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
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<br>
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<br>
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<a name="2.1.3.4 Parameters For Multi-Core Systems"></a>
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<h4>2.1.3.4 Parameters For Multi-Core Systems</h4>
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In addition to the define file, two Verilog parameters are available to facilitate software development on multi-core systems.<br>
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For example, in a dual-core openMSP430 system, the cores can be instantiated as following:
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<br>
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<br>
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br></td>
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<td bgcolor="#d0d0d0" width="3"><br></td>
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<td width="15"><br></td>
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<td>
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<code>
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openMSP430 #(.INST_NR (<strong>0</strong>), .TOTAL_NR(<strong>1</strong>)) openMSP430_core_0 (
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<br>...
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<br>);
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<br>
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<br>openMSP430 #(.INST_NR (<strong>1</strong>), .TOTAL_NR(<strong>1</strong>)) openMSP430_core_1 (
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<br>...
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<br>);
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</code>
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</td>
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</tr>
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</tbody>
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</table>
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<br>
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The values of these parameters are then directly accessible through the CPU_NR register of the SFR peripheral.<br>
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For example, if both cores share the same program memory, the software can take advantage of this information as following:
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<br><br>
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<td width="35"><br></td>
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<td bgcolor="#d0d0d0" width="3"><br></td>
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<td width="15"><br></td>
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<td>
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<code>
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"...
|
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<br>int main(void) {
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<br> if (CPU_NR==<strong>0x0100</strong>) {
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<br> main_core_0(); // Main routine call for core 0
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<br> }
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<br> if (CPU_NR==<strong>0x0101</strong>) {
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<br> main_core_1(); // Main routine call for core 1
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<br> }
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<br>}
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<br>..."
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</code>
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</td>
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</tr>
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</tbody>
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</table>
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<br><br>
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<br><br>
|
|
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<a name="2.1.4 Memory mapping"></a>
|
<a name="2.1.4 Memory mapping"></a>
|
<h3>2.1.4 Memory mapping</h3>
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<h3>2.1.4 Memory mapping</h3>
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| Line 778... |
Line 896... |
<td> Input </td>
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<td> Input </td>
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<td> 1 </td>
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<td> 1 </td>
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<td style="vertical-align: top; text-align: center;"><async><br>
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<td style="vertical-align: top; text-align: center;"><async><br>
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</td>
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</td>
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<td> Debug interface: UART RXD (asynchronous) </td>
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<td> Debug interface: UART RXD (asynchronous) </td>
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</tr><tr align="center">
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</tr><tr>
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<td style="vertical-align: top;">dbg_i2c_addr<br>
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</td>
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<td style="vertical-align: top;"> Input</td>
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<td style="vertical-align: top;"> 7</td>
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<td style="vertical-align: top; text-align: center;">mclk</td>
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<td style="vertical-align: top;">Debug interface: I2C Address<br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">dbg_i2c_broadcast<br>
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</td>
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<td style="vertical-align: top;"> Input</td>
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<td style="vertical-align: top;"> 7</td>
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<td style="vertical-align: top; text-align: center;">mclk</td>
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<td style="vertical-align: top;">Debug interface: I2C Broadcast Address (for multicore systems)<br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">dbg_i2c_scl<br>
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</td>
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<td style="vertical-align: top;"> Input</td>
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<td style="vertical-align: top;"> 1</td>
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<td style="vertical-align: top; text-align: center;"><async></td>
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<td style="vertical-align: top;">Debug interface: I2C SCL (asynchronous)</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">dbg_i2c_sda_in<br>
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</td>
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<td style="vertical-align: top;"> Input</td>
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<td style="vertical-align: top;"> 1</td>
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<td style="vertical-align: top; text-align: center;"><async></td>
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<td style="vertical-align: top;">Debug interface: I2C SDA IN (asynchronous)</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">dbg_i2c_sda_out<br>
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</td>
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<td style="vertical-align: top;"> Output</td>
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<td style="vertical-align: top;"> 1</td>
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<td style="vertical-align: top; text-align: center;">mclk</td>
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<td style="vertical-align: top;">Debug interface: I2C SDA OUT<br>
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</td>
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</tr>
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<tr align="center">
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<td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
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<td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td style="vertical-align: top;">scan_enable<br>
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<td style="vertical-align: top;">scan_enable<br>
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</td>
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</td>
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| Line 908... |
Line 1069... |
<a name="2.1.7 Serial Debug Interface"></a>
|
<a name="2.1.7 Serial Debug Interface"></a>
|
<h3>2.1.7 Serial Debug Interface</h3>
|
<h3>2.1.7 Serial Debug Interface</h3>
|
|
|
All the details about the Serial Debug Interface are located <a href="http://opencores.org/project,openmsp430,serial%20debug%20interface">here</a>.<br>
|
All the details about the Serial Debug Interface are located <a href="http://opencores.org/project,openmsp430,serial%20debug%20interface">here</a>.<br>
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<br>
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<br>
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<a name="2.1.8 Benchmark results"></a>
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<h3>2.1.8 Benchmark results</h3>
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<a name="2.1.8.1 Dhrystone"></a>
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<h4>2.1.8.1 Dhrystone (DMIPS/MHz)</h4>
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Dhrystone is known for being susceptible to compiler optimizations (among other issues).<br>However,
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as it is still quite a popular metric, some results are provided here
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(ranging from 0.30 to 0.45 DMIPS/MHz depending on the compiler version
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and options).<br>
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Note that the used C-code is available in the repository <a href="http://opencores.org/websvn,listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fdhrystone_v2.1%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_dhrystone_v2.1_">here</a> and <a href="http://opencores.org/websvn,listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fdhrystone_4mcu%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_dhrystone_4mcu_">here</a>.<br>
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<br>
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<table style="text-align: left; width: 40%;" border="1" cellpadding="2" cellspacing="2">
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<tbody>
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<tr>
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<td style="text-align: center;" colspan="1" rowspan="2"><span style="font-weight: bold;">Dhrystone flavor</span></td>
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<td style="font-weight: bold; text-align: right;">Compiler options</td>
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<td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-Os</td>
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<td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O2</td>
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<td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O3</td>
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</tr>
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<tr align="left">
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<td style="font-weight: bold;">Compiler version
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</td>
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</tr>
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<tr>
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<td style="text-align: center;" colspan="1" rowspan="2">Dhrystone v2.1<br>
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(<a href="http://ftp.unicamp.br/pub/unix-c/benchmark/system/">common version</a>)</td>
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<td style="text-align: left;">mspgcc v4.4.5</td>
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<td style="text-align: center;">0.30</td>
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<td style="text-align: center;">0.32</td>
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<td style="text-align: center;">0.33</td>
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</tr>
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<tr>
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<td style="text-align: left;">mspgcc v4.6.3</td>
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<td style="text-align: center;">0.37</td>
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<td style="text-align: center;">0.39</td>
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<td style="text-align: center;">0.40</td>
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</tr>
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<tr>
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<td style="text-align: center;" colspan="1" rowspan="2">Dhrystone v2.1<br>
|
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(<a href="http://www.ecrostech.com/Other/Resources/Dhrystone.htm">MCU adapted</a>)</td>
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<td style="text-align: left;">mspgcc v4.4.5</td>
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<td style="text-align: center;">0.30</td>
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<td style="text-align: center;">0.30</td>
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<td style="text-align: center;">0.31</td>
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</tr>
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<tr>
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<td style="text-align: left;">mspgcc v4.6.3</td>
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<td style="text-align: center;">0.37</td>
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<td style="text-align: center;">0.44</td>
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<td style="text-align: center;">0.45</td>
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</tr>
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</tbody>
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</table>
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|
|
|
<a name="2.1.8.2 CoreMark"></a>
|
|
<h4>2.1.8.2 CoreMark (CoreMark/MHz)</h4>
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|
CoreMark tries to address most of Dhrystone's pitfall by preventing the
|
|
compiler to optimize some code away and using "real-life" algorithm.<br>
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|
Note that the used C-code is available in the repository <a href="http://opencores.org/websvn,listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fcoremark_v1.0%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_coremark_v1.0_">here</a>.<br>
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<br>
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<table style="text-align: left; width: 40%;" border="1" cellpadding="2" cellspacing="2">
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<tbody>
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<tr>
|
|
<td style="text-align: center;" colspan="1" rowspan="2"><br>
|
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</td>
|
|
<td style="font-weight: bold; text-align: right;">Compiler options</td>
|
|
<td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-Os</td>
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|
<td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O2</td>
|
|
<td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O3</td>
|
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</tr>
|
|
<tr align="left">
|
|
<td style="font-weight: bold;">Compiler version</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="text-align: center;" colspan="1" rowspan="2">CoreMark v1.0<br>
|
|
(<a href="http://www.coremark.org/">official version</a>)</td>
|
|
<td style="text-align: left;">mspgcc v4.4.5</td>
|
|
<td style="text-align: center;">0.78</td>
|
|
<td style="text-align: center;">0.85</td>
|
|
<td style="text-align: center;">0.83</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="text-align: left;">mspgcc v4.6.3</td>
|
|
<td style="text-align: center;">0.74</td>
|
|
<td style="text-align: center;">0.91</td>
|
|
<td style="text-align: center;">0.87</td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<br>
|
|
|
<a name="2.2_System_Peripherals"></a>
|
<a name="2.2_System_Peripherals"></a>
|
<h2>2.2 System Peripherals</h2>
|
<h2>2.2 System Peripherals</h2>
|
In addition to the CPU core itself, several peripherals are also
|
In addition to the CPU core itself, several peripherals are also
|
provided and can be easily connected to the core during integration.
|
provided and can be easily connected to the core during integration.
|
The followings are directly integrated within the core because of their
|
The followings are directly integrated within the core because of their
|
| Line 1064... |
Line 1320... |
</table>
|
</table>
|
<br>
|
<br>
|
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
|
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
|
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
|
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
|
<br>
|
<br>
|
In addition, two 16-bit read-only registers have been added in order
|
In addition, three 16-bit read-only registers have been added in order
|
to let the software know with which version of the openMSP430 it is
|
to let the software know with which version of the openMSP430 it is
|
running:<br>
|
running:<br>
|
<br>
|
<br>
|
<table border="1">
|
<table border="1">
|
|
|
| Line 1099... |
Line 1355... |
<td><small>CPU_ID_HI</small></td>
|
<td><small>CPU_ID_HI</small></td>
|
<td><small>0x0006</small></td>
|
<td><small>0x0006</small></td>
|
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
|
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
|
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
|
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
|
<td colspan="1"><font size="-5">MPY</font></td>
|
<td colspan="1"><font size="-5">MPY</font></td>
|
|
</tr><tr>
|
|
<td style="vertical-align: top; text-align: center;"><small>CPU_NR</small></td>
|
|
<td style="vertical-align: top; text-align: center;"><small>0x0008</small></td>
|
|
<td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_TOTAL_NR</font></td>
|
|
<td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_INST_NR</font></td>
|
</tr>
|
</tr>
|
|
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<table border="0">
|
<table border="0">
|
|
|
| Line 1134... |
Line 1396... |
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
|
<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
|
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
|
<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
|
</tr>
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>CPU_INST_NR</b></li></td>
|
|
<td>: Current oMSP instance number (for multicore systems)</td>
|
|
</tr>
|
|
<tr>
|
|
<td> </td><td valign="top"><li><b>CPU_TOTAL_NR</b></li></td>
|
|
<td>: Total number of oMSP instances-1 (for multicore systems)</td>
|
|
</tr>
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span> and <span style="font-style: italic;">CPU_ID_HI</span> are identical to the Serial Debug Interface register counterparts.<br>
|
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span>, <span style="font-style: italic;">CPU_ID_HI</span> and <span style="font-style: italic;">CPU_NR</span> are identical to the Serial Debug Interface register counterparts.<br>
|
<a name="2.2.2 Watchdog Timer"></a>
|
<a name="2.2.2 Watchdog Timer"></a>
|
<h3>2.2.4 Watchdog Timer</h3>
|
<h3>2.2.4 Watchdog Timer</h3>
|
|
|
|
|
|
|
