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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
<html><head><title>openMSP430 Core</title></head><body>
<html><head><title>openMSP430 Core</title></head>
 
<body>
<h3>Table of content</h3>
<h3>Table of content</h3>
<ul>
<ul>
        <li><a href="#1.%20Introduction">1. Introduction</a></li>
        <li><a href="#1.%20Introduction">1. Introduction</a></li>
        <li><a href="#2.%20Design">      2. Design</a>
        <li><a href="#2.%20Design">      2. Design</a>
        <ul>
        <ul>
Line 12... Line 13...
           <li><a href="#2.1.3%20Configuration">                 2.1.3 Configuration</a></li>
           <li><a href="#2.1.3%20Configuration">                 2.1.3 Configuration</a></li>
           <ul>
           <ul>
                <li><a href="#2.1.3.1%20Basic%20System%20Configuration">    2.1.3.1 Basic System Configuration</a></li>
                <li><a href="#2.1.3.1%20Basic%20System%20Configuration">    2.1.3.1 Basic System Configuration</a></li>
                <li><a href="#2.1.3.2%20Advanced%20System%20Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
                <li><a href="#2.1.3.2%20Advanced%20System%20Configuration"> 2.1.3.2 Advanced System Configuration</a></li>
                <li><a href="#2.1.3.3%20Expert%20System%20Configuration">   2.1.3.3 Expert System Configuration</a></li>
                <li><a href="#2.1.3.3%20Expert%20System%20Configuration">   2.1.3.3 Expert System Configuration</a></li>
 
                <li><a href="#2.1.3.4%20Parameters%20For%20Multi-Core%20Systems"> 2.1.3.4 Parameters For Multi-Core Systems</a></li>
           </ul>
           </ul>
           <li><a href="#2.1.4%20Memory%20mapping">                2.1.4 Memory mapping</a></li>
           <li><a href="#2.1.4%20Memory%20mapping">                2.1.4 Memory mapping</a></li>
           <li><a href="#2.1.5%20Pinout">                        2.1.5 Pinout</a></li>
           <li><a href="#2.1.5%20Pinout">                        2.1.5 Pinout</a></li>
           <li><a href="#2.1.6%20Instruction%20Cycles%20and%20Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
           <li><a href="#2.1.6%20Instruction%20Cycles%20and%20Lengths">2.1.6 Instruction Cycles and Lengths</a></li>
           <li><a href="#2.1.7%20Serial%20Debug%20Interface">        2.1.7 Serial Debug Interface</a></li>
           <li><a href="#2.1.7%20Serial%20Debug%20Interface">        2.1.7 Serial Debug Interface</a></li>
 
           <li><a href="#2.1.8%20Benchmark%20results"> 2.1.8 Benchmark results</a></li>
 
           <ul>
 
                <li><a href="#2.1.8.1%20Dhrystone">2.1.8.1 Dhrystone</a></li>
 
                <li><a href="#2.1.8.2%20CoreMark">2.1.8.2 CoreMark</a></li>
 
           </ul>
                </ul>
                </ul>
           </li>
           </li>
      <li><a href="#2.2_System_Peripherals">        2.2 System Peripherals</a>
      <li><a href="#2.2_System_Peripherals">        2.2 System Peripherals</a>
 
 
        <ul>
        <ul>
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<a name="2.1.1 Design structure"></a>
<a name="2.1.1 Design structure"></a>
<h3>2.1.1 Design structure</h3>
<h3>2.1.1 Design structure</h3>
 
 
The following diagram shows the openMSP430 design structure:
The following diagram shows the openMSP430 design structure:
<br><br>
<br><br>
<img src="usercontent,img,1267738921" alt="CPU Structure" title="CPU Structure" width="80%">
<img src="http://opencores.org/usercontent,img,1354053264" alt="CPU Structure" title="CPU Structure" width="80%">
<br>
<br>
<ul>
<ul>
        <li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
        <li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
        <li><b>Execution unit</b>:
        <li><b>Execution unit</b>:
Containing the ALU and the register file, this module executes the
Containing the ALU and the register file, this module executes the
current decoded instruction according to the execution state.</li>
current decoded instruction according to the execution state.</li>
        <li><b>Serial Debug Interface</b>:
        <li><b>Serial Debug Interface</b>:
Contains all the required logic for a Nexus class 3 debugging unit
Contains all the required logic for a Nexus class 3 debugging unit
(without trace). Communication with the host is done with a standard
(without trace). Communication with the host is performed with a standard
two-wire 8N1 serial interface.</li>
two-wire interface following either the UART 8N1 or I<sup>2</sup>C serial protocol.</li>
   <li><b>Memory backbone</b>: This block
   <li><b>Memory backbone</b>: This block
performs a simple arbitration between the frontend and execution-unit
performs a simple arbitration between the frontend and execution-unit
for program, data and peripheral memory access.</li>
for program, data and peripheral memory access.</li>
   <li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
   <li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
   <li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
   <li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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      <br>
      <br>
// Program Memory Size:<br>
// Program Memory Size:<br>
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Uncomment the required memory size<br>
Uncomment the required memory size<br>
//-------------------------------------------------------<br>
//-------------------------------------------------------<br>
 
//`define PMEM_SIZE_CUSTOM<br>
//`define PMEM_SIZE_59_KB<br>
//`define PMEM_SIZE_59_KB<br>
//`define PMEM_SIZE_55_KB<br>
//`define PMEM_SIZE_55_KB<br>
//`define PMEM_SIZE_54_KB<br>
//`define PMEM_SIZE_54_KB<br>
//`define PMEM_SIZE_51_KB<br>
//`define PMEM_SIZE_51_KB<br>
//`define PMEM_SIZE_48_KB<br>
//`define PMEM_SIZE_48_KB<br>
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      <br>
      <br>
// Data Memory Size:<br>
// Data Memory Size:<br>
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Uncomment the required memory size<br>
Uncomment the required memory size<br>
//-------------------------------------------------------<br>
//-------------------------------------------------------<br>
 
//`define DMEM_SIZE_CUSTOM<br>
//`define DMEM_SIZE_32_KB<br>
//`define DMEM_SIZE_32_KB<br>
//`define DMEM_SIZE_24_KB<br>
//`define DMEM_SIZE_24_KB<br>
//`define DMEM_SIZE_16_KB<br>
//`define DMEM_SIZE_16_KB<br>
//`define DMEM_SIZE_10_KB<br>
//`define DMEM_SIZE_10_KB<br>
//`define DMEM_SIZE_8_KB<br>
//`define DMEM_SIZE_8_KB<br>
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<ul>
<ul>
        <li>Make sure that the program and data memories have the correct size :-P</li>
        <li>Make sure that the program and data memories have the correct size :-P</li>
        <li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
        <li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
</ul>
</ul>
<br>
<br>
 
<b><u>Note:</u></b> when selected, custom memory sizes can be specified in the "Expert System Configuration" section.
 
<br>
 
<br>
 
 
<a name="2.1.3.2 Advanced System Configuration"></a>
<a name="2.1.3.2 Advanced System Configuration"></a>
<h4>2.1.3.2 Advanced System Configuration</h4>
<h4>2.1.3.2 Advanced System Configuration</h4>
 
 
In this section, some additional features are available in order to match the needs of more experienced users.
In this section, some additional features are available in order to match the needs of more experienced users.
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// up to 32 kB (i.e. from 0x0000 to 0x7fff).<br>
// up to 32 kB (i.e. from 0x0000 to 0x7fff).<br>
// As a consequence, the data memory mapping will be<br>
// As a consequence, the data memory mapping will be<br>
// shifted up and a custom linker script will therefore<br>
// shifted up and a custom linker script will therefore<br>
// be required by the GCC compiler.<br>
// be required by the GCC compiler.<br>
//-------------------------------------------------------<br>
//-------------------------------------------------------<br>
 
//`define PER_SIZE_CUSTOM<br>
//`define PER_SIZE_32_KB<br>
//`define PER_SIZE_32_KB<br>
//`define PER_SIZE_16_KB<br>
//`define PER_SIZE_16_KB<br>
//`define PER_SIZE_8_KB<br>
//`define PER_SIZE_8_KB<br>
//`define PER_SIZE_4_KB<br>
//`define PER_SIZE_4_KB<br>
//`define PER_SIZE_2_KB<br>
//`define PER_SIZE_2_KB<br>
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is and if you don't want to know what it is, you should probably not
is and if you don't want to know what it is, you should probably not
modify this section.</li>
modify this section.</li>
        <li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
        <li>The sum of program, data and peripheral memory space <b>MUST NOT</b> exceed 64 kB</li>
</ul>
</ul>
<br>
<br>
 
<b><u>Note:</u></b> when selected, custom peripheral memory space can be specified in the "Expert System Configuration" section.
 
<br>
 
<br>
<a name="2.1.3.3 Expert System Configuration"></a>
<a name="2.1.3.3 Expert System Configuration"></a>
<h4>2.1.3.3 Expert System Configuration</h4>
<h4>2.1.3.3 Expert System Configuration</h4>
In this section, you will find configuration options which are
In this section, you will find configuration options which are
relevant for roughly 0.1% of the users (according to a highly
relevant for roughly 0.1% of the users (according to a highly
reliable market analysis ;-) ).
reliable market analysis ;-) ).
Line 343... Line 359...
you have a good reason to do so... and if you know what<br>
you have a good reason to do so... and if you know what<br>
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; you are doing :-P<br>
//&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; you are doing :-P<br>
//<br>
//<br>
//============================================================================<br>
//============================================================================<br>
      <br>
      <br>
 
//-------------------------------------------------------<br>
 
// Select serial debug interface protocol<br>
 
//-------------------------------------------------------<br>
 
//&nbsp;&nbsp;&nbsp; DBG_UART -&gt; Enable UART (8N1) debug interface<br>
 
//&nbsp;&nbsp;&nbsp; DBG_I2C&nbsp; -&gt; Enable I2C debug interface<br>
 
//-------------------------------------------------------<br>
 
`define DBG_UART<br>
 
//`define DBG_I2C<br>
 
      <br>
 
      <br>
 
//-------------------------------------------------------<br>
 
// Enable the I2C broadcast address<br>
 
//-------------------------------------------------------<br>
 
// For multicore systems, a common I2C broadcast address<br>
 
// can be given to all oMSP cores in order to<br>
 
// synchronously RESET, START, STOP, or STEP all CPUs<br>
 
// at once with a single I2C command.<br>
 
// If you have a single openMSP430 in your system,<br>
 
// this option can stay commented-out.<br>
 
//-------------------------------------------------------<br>
 
//`define DBG_I2C_BROADCAST<br>
 
      <br>
 
<br>
//-------------------------------------------------------<br>// Number of hardware breakpoint/watchpoint units<br>
//-------------------------------------------------------<br>// Number of hardware breakpoint/watchpoint units<br>
// (each unit contains two hardware addresses available<br>
// (each unit contains two hardware addresses available<br>
// for breakpoints or watchpoints):<br>
// for breakpoints or watchpoints):<br>
//&nbsp;&nbsp; - DBG_HWBRK_0 -&gt; Include hardware breakpoints unit 0<br>
//&nbsp;&nbsp; - DBG_HWBRK_0 -&gt; Include hardware breakpoints unit 0<br>
//&nbsp;&nbsp; - DBG_HWBRK_1 -&gt; Include hardware breakpoints unit 1<br>
//&nbsp;&nbsp; - DBG_HWBRK_1 -&gt; Include hardware breakpoints unit 1<br>
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//-------------------------------------------------------<br>
//-------------------------------------------------------<br>
//`define DBG_HWBRK_RANGE<br>
//`define DBG_HWBRK_RANGE<br>
      <br>
      <br>
      <br>
      <br>
//-------------------------------------------------------<br>
//-------------------------------------------------------<br>
 
// Custom Program/Data and Peripheral Memory Spaces<br>
 
//-------------------------------------------------------<br>
 
// The following values are valid only if the<br>
 
// corresponding *_SIZE_CUSTOM defines are uncommented:<br>
 
//<br>
 
//  - *_SIZE   : size of the section in bytes.<br>
 
//  - *_AWIDTH : address port width, this value must allow<br>
 
//               to address all WORDS of the section<br>
 
//               (i.e. the *_SIZE divided by 2)<br>
 
//-------------------------------------------------------<br>
 
<br>
 
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)<br>
 
`define PMEM_CUSTOM_AWIDTH      10<br>
 
`define PMEM_CUSTOM_SIZE      2048<br>
 
<br>
 
// Custom Data memory    (enabled with DMEM_SIZE_CUSTOM)<br>
 
`define DMEM_CUSTOM_AWIDTH       6<br>
 
`define DMEM_CUSTOM_SIZE       128<br>
 
<br>
 
// Custom Peripheral memory  (enabled with PER_SIZE_CUSTOM)<br>
 
`define PER_CUSTOM_AWIDTH        8<br>
 
`define PER_CUSTOM_SIZE        512<br>
 
<br>
 
<br>
 
//-------------------------------------------------------<br>
// ASIC version<br>
// ASIC version<br>
//-------------------------------------------------------<br>
//-------------------------------------------------------<br>
// When uncommented, this define will enable the<br>
// When uncommented, this define will enable the<br>
// ASIC system configuration section (see below) and<br>
// ASIC system configuration section (see below) and<br>
// will activate scan support for production test.<br>
// will activate scan support for production test.<br>
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<ul>
<ul>
        <li>This is the expert section... so you know what your are doing anyway right ;-)</li>
        <li>This is the expert section... so you know what your are doing anyway right ;-)</li>
</ul>
</ul>
<br>
<br>
All remaining defines located after the ASIC section in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
All remaining defines located after the ASIC section in the <b><i>openMSP430_defines.v</i></b> file are system constants and <b>MUST NOT</b> be edited.
 
<br>
 
<br>
 
<a name="2.1.3.4 Parameters For Multi-Core Systems"></a>
 
<h4>2.1.3.4 Parameters For Multi-Core Systems</h4>
 
 
 
In addition to the define file, two Verilog parameters are available to facilitate software development on multi-core systems.<br>
 
For example, in a dual-core openMSP430 system, the cores can be instantiated as following:
 
<br>
 
<br>
 
<table border="0" cellpadding="0" cellspacing="4">
 
<tbody><tr>
 
<td width="35"><br></td>
 
<td bgcolor="#d0d0d0" width="3"><br></td>
 
<td width="15"><br></td>
 
<td>
 
        <code>
 
                          openMSP430 #(.INST_NR (<strong>0</strong>), .TOTAL_NR(<strong>1</strong>)) openMSP430_core_0 (
 
                      <br>...
 
                      <br>);
 
                      <br>
 
                      <br>openMSP430 #(.INST_NR (<strong>1</strong>), .TOTAL_NR(<strong>1</strong>)) openMSP430_core_1 (
 
                      <br>...
 
                      <br>);
 
        </code>
 
</td>
 
</tr>
 
</tbody>
 
</table>
 
<br>
 
The values of these parameters are then directly accessible through the CPU_NR register of the SFR peripheral.<br>
 
For example, if both cores share the same program memory, the software can take advantage of this information as following:
 
<br><br>
 
<table border="0" cellpadding="0" cellspacing="4">
 
<tbody><tr>
 
<td width="35"><br></td>
 
<td bgcolor="#d0d0d0" width="3"><br></td>
 
<td width="15"><br></td>
 
<td>
 
        <code>
 
                           "...
 
                      <br>int main(void) {
 
                      <br>&nbsp;&nbsp;if (CPU_NR==<strong>0x0100</strong>) {
 
                      <br>&nbsp;&nbsp;&nbsp;&nbsp;main_core_0();&nbsp;// Main routine call for core 0
 
                      <br>&nbsp;&nbsp;}
 
                      <br>&nbsp;&nbsp;if (CPU_NR==<strong>0x0101</strong>) {
 
                      <br>&nbsp;&nbsp;&nbsp;&nbsp;main_core_1();&nbsp;// Main routine call for core 1
 
                      <br>&nbsp;&nbsp;}
 
                      <br>}
 
                      <br>..."
 
        </code>
 
</td>
 
</tr>
 
</tbody>
 
</table>
<br><br>
<br><br>
 
 
<a name="2.1.4 Memory mapping"></a>
<a name="2.1.4 Memory mapping"></a>
<h3>2.1.4 Memory mapping</h3>
<h3>2.1.4 Memory mapping</h3>
 
 
Line 778... Line 896...
             <td> Input                                                            </td>
             <td> Input                                                            </td>
             <td> 1                                                                </td>
             <td> 1                                                                </td>
             <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
             <td style="vertical-align: top; text-align: center;">&lt;async&gt;<br>
      </td>
      </td>
<td> Debug interface: UART RXD (asynchronous)                         </td>
<td> Debug interface: UART RXD (asynchronous)                         </td>
        </tr><tr align="center">
        </tr><tr>
 
      <td style="vertical-align: top;">dbg_i2c_addr<br>
 
      </td>
 
      <td style="vertical-align: top;"> Input</td>
 
      <td style="vertical-align: top;"> 7</td>
 
      <td style="vertical-align: top; text-align: center;">mclk</td>
 
      <td style="vertical-align: top;">Debug interface: I2C Address<br>
 
      </td>
 
    </tr>
 
    <tr>
 
      <td style="vertical-align: top;">dbg_i2c_broadcast<br>
 
      </td>
 
      <td style="vertical-align: top;"> Input</td>
 
      <td style="vertical-align: top;"> 7</td>
 
      <td style="vertical-align: top; text-align: center;">mclk</td>
 
      <td style="vertical-align: top;">Debug interface: I2C Broadcast Address (for multicore systems)<br>
 
      </td>
 
    </tr>
 
    <tr>
 
      <td style="vertical-align: top;">dbg_i2c_scl<br>
 
      </td>
 
      <td style="vertical-align: top;"> Input</td>
 
      <td style="vertical-align: top;"> 1</td>
 
      <td style="vertical-align: top; text-align: center;">&lt;async&gt;</td>
 
      <td style="vertical-align: top;">Debug interface: I2C SCL (asynchronous)</td>
 
    </tr>
 
    <tr>
 
      <td style="vertical-align: top;">dbg_i2c_sda_in<br>
 
      </td>
 
      <td style="vertical-align: top;"> Input</td>
 
      <td style="vertical-align: top;"> 1</td>
 
      <td style="vertical-align: top; text-align: center;">&lt;async&gt;</td>
 
      <td style="vertical-align: top;">Debug interface: I2C SDA IN (asynchronous)</td>
 
    </tr>
 
    <tr>
 
      <td style="vertical-align: top;">dbg_i2c_sda_out<br>
 
      </td>
 
      <td style="vertical-align: top;"> Output</td>
 
      <td style="vertical-align: top;"> 1</td>
 
      <td style="vertical-align: top; text-align: center;">mclk</td>
 
      <td style="vertical-align: top;">Debug interface: I2C SDA OUT<br>
 
      </td>
 
    </tr>
 
<tr align="center">
      <td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
      <td colspan="5" rowspan="1" style="vertical-align: top;"><b><i>Scan</i></b></td>
    </tr>
    </tr>
    <tr>
    <tr>
      <td style="vertical-align: top;">scan_enable<br>
      <td style="vertical-align: top;">scan_enable<br>
      </td>
      </td>
Line 908... Line 1069...
<a name="2.1.7 Serial Debug Interface"></a>
<a name="2.1.7 Serial Debug Interface"></a>
<h3>2.1.7 Serial Debug Interface</h3>
<h3>2.1.7 Serial Debug Interface</h3>
 
 
All the details about the Serial Debug Interface are located <a href="http://opencores.org/project,openmsp430,serial%20debug%20interface">here</a>.<br>
All the details about the Serial Debug Interface are located <a href="http://opencores.org/project,openmsp430,serial%20debug%20interface">here</a>.<br>
<br>
<br>
 
 
 
<a name="2.1.8 Benchmark results"></a>
 
<h3>2.1.8 Benchmark results</h3>
 
 
 
<a name="2.1.8.1 Dhrystone"></a>
 
<h4>2.1.8.1 Dhrystone (DMIPS/MHz)</h4>
 
Dhrystone is known for being susceptible to compiler optimizations (among other issues).<br>However,
 
as it is still quite a popular metric, some results are provided here
 
(ranging from 0.30 to 0.45 DMIPS/MHz depending on the compiler version
 
and options).<br>
 
Note that the used C-code is available in the repository <a href="http://opencores.org/websvn,listing?repname=openmsp430&amp;path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fdhrystone_v2.1%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_dhrystone_v2.1_">here</a> and <a href="http://opencores.org/websvn,listing?repname=openmsp430&amp;path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fdhrystone_4mcu%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_dhrystone_4mcu_">here</a>.<br>
 
<br>
 
 
 
<table style="text-align: left; width: 40%;" border="1" cellpadding="2" cellspacing="2">
 
  <tbody>
 
    <tr>
 
      <td style="text-align: center;" colspan="1" rowspan="2"><span style="font-weight: bold;">Dhrystone flavor</span></td>
 
      <td style="font-weight: bold; text-align: right;">Compiler options</td>
 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-Os</td>
 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O2</td>
 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O3</td>
 
    </tr>
 
    <tr align="left">
 
      <td style="font-weight: bold;">Compiler version
 
      </td>
 
    </tr>
 
    <tr>
 
      <td style="text-align: center;" colspan="1" rowspan="2">Dhrystone v2.1<br>
 
                     (<a href="http://ftp.unicamp.br/pub/unix-c/benchmark/system/">common version</a>)</td>
 
      <td style="text-align: left;">mspgcc v4.4.5</td>
 
      <td style="text-align: center;">0.30</td>
 
      <td style="text-align: center;">0.32</td>
 
      <td style="text-align: center;">0.33</td>
 
    </tr>
 
    <tr>
 
      <td style="text-align: left;">mspgcc v4.6.3</td>
 
      <td style="text-align: center;">0.37</td>
 
      <td style="text-align: center;">0.39</td>
 
      <td style="text-align: center;">0.40</td>
 
    </tr>
 
    <tr>
 
      <td style="text-align: center;" colspan="1" rowspan="2">Dhrystone v2.1<br>
 
                     (<a href="http://www.ecrostech.com/Other/Resources/Dhrystone.htm">MCU adapted</a>)</td>
 
      <td style="text-align: left;">mspgcc v4.4.5</td>
 
      <td style="text-align: center;">0.30</td>
 
      <td style="text-align: center;">0.30</td>
 
      <td style="text-align: center;">0.31</td>
 
    </tr>
 
    <tr>
 
      <td style="text-align: left;">mspgcc v4.6.3</td>
 
      <td style="text-align: center;">0.37</td>
 
      <td style="text-align: center;">0.44</td>
 
      <td style="text-align: center;">0.45</td>
 
    </tr>
 
  </tbody>
 
</table>
 
 
 
<a name="2.1.8.2 CoreMark"></a>
 
<h4>2.1.8.2 CoreMark (CoreMark/MHz)</h4>
 
CoreMark tries to address most of Dhrystone's pitfall by preventing the
 
compiler to optimize some code away and using "real-life" algorithm.<br>
 
Note that the used C-code is available in the repository <a href="http://opencores.org/websvn,listing?repname=openmsp430&amp;path=%2Fopenmsp430%2Ftrunk%2Fcore%2Fsim%2Frtl_sim%2Fsrc-c%2Fcoremark_v1.0%2F#path_openmsp430_trunk_core_sim_rtl_sim_src-c_coremark_v1.0_">here</a>.<br>
 
<br>
 
 
 
<table style="text-align: left; width: 40%;" border="1" cellpadding="2" cellspacing="2">
 
  <tbody>
 
    <tr>
 
      <td style="text-align: center;" colspan="1" rowspan="2"><br>
 
</td>
 
      <td style="font-weight: bold; text-align: right;">Compiler options</td>
 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-Os</td>
 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O2</td>
 
      <td colspan="1" rowspan="2" style="vertical-align: top; text-align: center; font-weight: bold;">-O3</td>
 
    </tr>
 
    <tr align="left">
 
      <td style="font-weight: bold;">Compiler version</td>
 
    </tr>
 
    <tr>
 
      <td style="text-align: center;" colspan="1" rowspan="2">CoreMark v1.0<br>
 
                     (<a href="http://www.coremark.org/">official version</a>)</td>
 
      <td style="text-align: left;">mspgcc v4.4.5</td>
 
      <td style="text-align: center;">0.78</td>
 
      <td style="text-align: center;">0.85</td>
 
      <td style="text-align: center;">0.83</td>
 
    </tr>
 
    <tr>
 
      <td style="text-align: left;">mspgcc v4.6.3</td>
 
      <td style="text-align: center;">0.74</td>
 
      <td style="text-align: center;">0.91</td>
 
      <td style="text-align: center;">0.87</td>
 
    </tr>
 
  </tbody>
 
</table>
 
<br>
 
 
<a name="2.2_System_Peripherals"></a>
<a name="2.2_System_Peripherals"></a>
<h2>2.2 System Peripherals</h2>
<h2>2.2 System Peripherals</h2>
In addition to the CPU core itself, several peripherals are also
In addition to the CPU core itself, several peripherals are also
provided and can be easily connected to the core during integration.
provided and can be easily connected to the core during integration.
The followings are directly integrated within the core because of their
The followings are directly integrated within the core because of their
Line 1064... Line 1320...
</table>
</table>
<br>
<br>
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
<b><sup><font color="#ff0000">1</font></sup></b>: These fields are not available if the NMI is excluded (see <i>openMSP430_defines.v</i> )<br>
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
<b><sup><font color="#ff0000">2</font></sup></b>: These fields are not available if the Watchdog is excluded (see <i>openMSP430_defines.v</i> )<br>
<br>
<br>
In addition, two 16-bit read-only registers have been added in order
In addition, three 16-bit read-only registers have been added in order
to let the software know with which version of the openMSP430 it is
to let the software know with which version of the openMSP430 it is
running:<br>
running:<br>
<br>
<br>
<table border="1">
<table border="1">
 
 
Line 1099... Line 1355...
<td><small>CPU_ID_HI</small></td>
<td><small>CPU_ID_HI</small></td>
<td><small>0x0006</small></td>
<td><small>0x0006</small></td>
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
<td colspan="1"><font size="-5">MPY</font></td>
<td colspan="1"><font size="-5">MPY</font></td>
 
</tr><tr>
 
      <td style="vertical-align: top; text-align: center;"><small>CPU_NR</small></td>
 
      <td style="vertical-align: top; text-align: center;"><small>0x0008</small></td>
 
      <td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_TOTAL_NR</font></td>
 
      <td colspan="8" rowspan="1" style="vertical-align: top; text-align: center;"><font size="-5">CPU_INST_NR</font></td>
</tr>
</tr>
 
 
</tbody>
</tbody>
</table>
</table>
<br>
<br>
<table border="0">
<table border="0">
 
 
Line 1134... Line 1396...
</tr>
</tr>
<tr>
<tr>
   <td>&nbsp;</td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
   <td>&nbsp;</td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
   <td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
   <td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
</tr>
</tr>
 
<tr>
 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_INST_NR</b></li></td>
 
   <td>: Current oMSP instance number (for multicore systems)</td>
 
</tr>
 
<tr>
 
   <td>&nbsp;</td><td valign="top"><li><b>CPU_TOTAL_NR</b></li></td>
 
   <td>: Total number of oMSP instances-1 (for multicore systems)</td>
 
</tr>
</tbody>
</tbody>
</table>
</table>
<br>
<br>
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span> and <span style="font-style: italic;">CPU_ID_HI</span> are identical to the Serial Debug Interface register counterparts.<br>
<span style="font-weight: bold; text-decoration: underline;">Note:</span> attentive readers will have noted that <span style="font-style: italic;">CPU_ID_LO</span>, <span style="font-style: italic;">CPU_ID_HI</span> and <span style="font-style: italic;">CPU_NR</span> are identical to the Serial Debug Interface register counterparts.<br>
<a name="2.2.2 Watchdog Timer"></a>
<a name="2.2.2 Watchdog Timer"></a>
<h3>2.2.4 Watchdog Timer</h3>
<h3>2.2.4 Watchdog Timer</h3>
 
 
 
 
 
 

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