| Line 68... |
Line 68... |
<a name="2.1 Design structure"></a>
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<a name="2.1 Design structure"></a>
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<h2>2.1 Design structure</h2>
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<h2>2.1 Design structure</h2>
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The following diagram shows the openMSP430 design structure:
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The following diagram shows the openMSP430 design structure:
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<br><br>
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<br><br>
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<img src="http://opencores.org/usercontent,img,1354053264" alt="CPU Structure" title="CPU Structure" width="80%">
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<img src="http://opencores.org/usercontent,img,1430426442" alt="CPU Structure" title="CPU Structure" width="80%">
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<br>
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<br>
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<ul>
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<ul>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Frontend</b>: This module performs the instruction Fetch and Decode tasks. It also contains the execution state machine.</li>
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<li><b>Execution unit</b>:
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<li><b>Execution unit</b>:
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Containing the ALU and the register file, this module executes the
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Containing the ALU and the register file, this module executes the
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Line 80... |
<li><b>Serial Debug Interface</b>:
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<li><b>Serial Debug Interface</b>:
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Contains all the required logic for a Nexus class 3 debugging unit
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Contains all the required logic for a Nexus class 3 debugging unit
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(without trace). Communication with the host is performed with a standard
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(without trace). Communication with the host is performed with a standard
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two-wire interface following either the UART 8N1 or I<sup>2</sup>C serial protocol.</li>
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two-wire interface following either the UART 8N1 or I<sup>2</sup>C serial protocol.</li>
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<li><b>Memory backbone</b>: This block
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<li><b>Memory backbone</b>: This block
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performs a simple arbitration between the frontend and execution-unit
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performs a simple arbitration between frontend, execution-unit, DMA and Serial-Debug interfaces
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for program, data and peripheral memory access.</li>
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for program, data and peripheral memory accesses.</li>
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<li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
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<li><b>Basic Clock Module</b>: Generates MCLK, ACLK, SMCLK and manage the low power modes.</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>SFRs</b>: The <b>S</b>pecial <b>F</b>unction <b>R</b>egister<b>s</b> block contain diverse configuration registers (NMI, Watchdog, ...).</li>
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<li><b>Watchdog</b>:
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<li><b>Watchdog</b>:
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Although it is a peripheral, the watchdog is directly included in
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Although it is a peripheral, the watchdog is directly included in
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the core because of its tight links with the NMI interrupts and PUC
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the core because of its tight links with the NMI interrupts and PUC
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// - Possibility to generate a software PUC reset<br>
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// - Possibility to generate a software PUC reset<br>
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//-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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`define WATCHDOG<br>
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`define WATCHDOG<br>
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<br>
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<br>
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<br>
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<br>
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///-------------------------------------------------------<br>
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//-------------------------------------------------------<br>
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// Include/Exclude DMA interface support<br>
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//-------------------------------------------------------<br>
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//`define DMA_IF_EN<br>
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<br>
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<br>
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//-------------------------------------------------------<br>
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// Include/Exclude Non-Maskable-Interrupt support<br>
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// Include/Exclude Non-Maskable-Interrupt support<br>
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//--------------------------------------------------------<br>
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//--------------------------------------------------------<br>
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`define NMI<br>
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`define NMI<br>
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<br>
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<br>
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<br>
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<br>
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Line 480... |
</td>
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</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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<br>
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<br>
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The values of these parameters are then directly accessible through the CPU_NR register of the SFR peripheral.<br>
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The values of these parameters are then directly accessible by software through the CPU_NR register of the SFR peripheral.<br>
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For example, if both cores share the same program memory, the software can take advantage of this information as following:
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For example, if both cores share the same program memory, the software can take advantage of this information as following:
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<br><br>
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<br><br>
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<table border="0" cellpadding="0" cellspacing="4">
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<table border="0" cellpadding="0" cellspacing="4">
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<tbody><tr>
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<tbody><tr>
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<td width="35"><br></td>
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<td width="35"><br></td>
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Line 524... |
between 512B and 32kB. As a consequence, the data memory space will be
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between 512B and 32kB. As a consequence, the data memory space will be
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shifted up, which means that the linker script of your favorite
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shifted up, which means that the linker script of your favorite
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toolchain will have to be modified accordingly.<br>
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toolchain will have to be modified accordingly.<br>
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The following schematic should hopefully illustrate this:<br>
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The following schematic should hopefully illustrate this:<br>
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<br><br>
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<br><br>
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<img src="usercontent,img,1306066277" alt="Memory mapping" title="Memory mapping" width="80%">
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<img src="http://opencores.org/usercontent,img,1306066277" alt="Memory mapping" title="Memory mapping" width="80%">
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<br>
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<br>
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<br><br>
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<br><br>
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<a name="2.5 Interrupt mapping"></a>
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<a name="2.5 Interrupt mapping"></a>
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<h2>2.5 Interrupt mapping</h2>
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<h2>2.5 Interrupt mapping</h2>
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Line 714... |
<td style="vertical-align: top; text-align: center;"><async><br>
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<td style="vertical-align: top; text-align: center;"><async><br>
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</td>
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</td>
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<td> Reset Pin (active low, asynchronous and non-glitchy) </td>
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<td> Reset Pin (active low, asynchronous and non-glitchy) </td>
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</tr>
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</tr>
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<tr> <td colspan="5" align="center"> <b><i>Interrupts</i></b> </td></tr>
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<tr>
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<td> irq </td>
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<td> Input </td>
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<td> `IRQ_NR-2<b><sup><font color="#ff0000">1</font></sup></b> </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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<td> Maskable interrupts (one-hot signal) </td>
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</tr>
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<tr>
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<td> nmi </td>
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<td> Input </td>
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<td> 1 </td>
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<td style="vertical-align: top; text-align: center;"><async><br>
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or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
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<td> Non-maskable interrupt (asynchronous and non-glitchy)<br>
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Set to 0 if unused.<br>
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</td>
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</tr>
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<tr>
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<td> irq_acc </td>
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<td> Output </td>
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<td> `IRQ_NR-2<b><sup><font color="#ff0000">1</font></sup></b> </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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<td> Interrupt request accepted (one-hot signal) </td>
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</tr>
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<tr> <td colspan="5" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
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<tr> <td colspan="5" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
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<tr>
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<tr>
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<td> pmem_addr </td>
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<td> pmem_addr </td>
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<td> Output </td>
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<td> Output </td>
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| Line 834... |
Line 867... |
<td> 2 </td>
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<td> 2 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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</td>
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<td> Peripheral write enable (high active) </td>
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<td> Peripheral write enable (high active) </td>
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</tr>
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</tr>
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<tr> <td colspan="5" align="center"> <b><i>Direct Memory Access interface</i></b> </td></tr>
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<tr> <td colspan="5" align="center"> <b><i>Interrupts</i></b> </td></tr>
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<tr>
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<tr>
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<td> irq </td>
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<td> dma_addr </td>
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<td> Input </td>
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<td> Input </td>
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<td> `IRQ_NR-2<b><sup><font color="#ff0000">1</font></sup></b> </td>
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<td> 15 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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</td>
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<td> Maskable interrupts (one-hot signal) </td>
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<td> Direct Memory Access address </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> nmi </td>
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<td> dma_din </td>
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<td> Input </td>
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<td> 16 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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<td> Direct Memory Access data input </td>
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</tr>
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<tr>
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<td> dma_dout </td>
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<td> Output </td>
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<td> 16 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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<td> Direct Memory Access data output </td>
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</tr>
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<tr>
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<td> dma_en </td>
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<td> Input </td>
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<td> Input </td>
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<td> 1 </td>
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<td> 1 </td>
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<td style="vertical-align: top; text-align: center;"><async><br>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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or mclk<b><sup><font color="#ff0000">4</font></sup></b></td>
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<td> Non-maskable interrupt (asynchronous and non-glitchy)<br>
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Set to 0 if unused.<br>
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</td>
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</td>
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<td> Direct Memory Access enable (high active) </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> irq_acc </td>
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<td> dma_priority </td>
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<td> Input </td>
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<td> 1 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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<td> Direct Memory Access priority (0:low / 1:high) </td>
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</tr>
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<tr>
|
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<td> dma_ready </td>
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<td> Output </td>
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<td> Output </td>
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<td> `IRQ_NR-2<b><sup><font color="#ff0000">1</font></sup></b> </td>
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<td> 1 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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</td>
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<td> Interrupt request accepted (one-hot signal) </td>
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<td> Direct Memory Access is complete </td>
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</tr>
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<tr>
|
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<td> dma_resp </td>
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<td> Output </td>
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<td> 1 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
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</td>
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<td> Direct Memory Access response (0:Okay / 1:Error) </td>
|
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</tr>
|
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<tr>
|
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<td> dma_we </td>
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<td> Input </td>
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<td> 2 </td>
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<td style="vertical-align: top; text-align: center;">mclk<br>
|
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</td>
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<td> Direct Memory Access write byte enable (high active) </td>
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</tr>
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<tr>
|
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<td> dma_wkup </td>
|
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<td> Input </td>
|
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<td> 1 </td>
|
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<td style="vertical-align: top; text-align: center;"><async><br>
|
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</td>
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<td> ASIC ONLY: DMA Wake-up (asynchronous and non-glitchy) </td>
|
</tr>
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</tr>
|
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<tr> <td colspan="5" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr> <td colspan="5" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
|
<tr>
|
<tr>
|
<td> dbg_en </td>
|
<td> dbg_en </td>
|
