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<html><head><title>openMSP430 File & Directory description</title></head><body>
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<title>openMSP430 File & Directory description</title>
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<body>
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<a name="TOC"></a>
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<a name="TOC"></a>
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<h3>Table of content</h3>
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<h3>Table of content</h3>
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<ul>
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<ul>
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<li><a href="#1. Introduction"> 1. Introduction</a></li>
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<li><a href="#1.%20Introduction"> 1. Introduction</a></li>
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<li><a href="#2. Directory structure: openMSP430 core"> 2. Directory structure: openMSP430 core</a></li>
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<li><a href="#2.%20Directory%20structure:%20openMSP430%20core"> 2. Directory structure: openMSP430 core</a></li>
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<li><a href="#3. Directory structure: FGPA projects"> 3. Directory structure: FGPA projects</a>
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<li><a href="#3.%20Directory%20structure:%20FGPA%20projects"> 3. Directory structure: FGPA projects</a>
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<ul>
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<ul>
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<li><a href="#3.1 Xilinx Spartan 3 example"> 3.1 Xilinx Spartan 3 example</a></li>
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<li><a href="#3.1%20Xilinx%20Spartan%203%20example"> 3.1 Xilinx Spartan 3 example</a></li>
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<li><a href="#3.2 Altera Cyclone II example"> 3.2 Altera Cyclone II example</a></li>
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<li><a href="#3.2%20Altera%20Cyclone%20II%20example"> 3.2 Altera Cyclone II example</a></li>
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<li><a href="#3.3%20Actel%20ProASIC3%20example"> 3.3 Actel ProASIC3 example</a></li>
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</ul>
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</ul>
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</li>
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</li>
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<li><a href="#4. Directory structure: Software Development Tools">4. Directory structure: Software Development Tools</a></li>
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<li><a href="#4.%20Directory%20structure:%20Software%20Development%20Tools">4. Directory structure: Software Development Tools</a></li>
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</ul>
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</ul>
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<a name="1. Introduction"></a>
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<a name="1. Introduction"></a>
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<h1>1. Introduction</h1>
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<h1>1. Introduction</h1>
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To simplify the integration of this IP, the directory structure is based on the <a href="http://www.opencores.org/downloads/opencores_coding_guidelines.pdf">OpenCores</a> recommendations.
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To simplify the integration of this IP, the directory structure is based on the <a href="http://www.opencores.org/downloads/opencores_coding_guidelines.pdf">OpenCores</a> recommendations.
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<br />
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<br>
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<a name="2. Directory structure: openMSP430 core"></a>
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<a name="2. Directory structure: openMSP430 core"></a>
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<div style="text-align: right"><a href="#TOC">Top</a></div>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>2. Directory structure: openMSP430 core</h1>
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<h1>2. Directory structure: openMSP430 core</h1>
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<table border="1">
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<table border="1">
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<tr><td colspan="5"><b>core</b></td> <td><i><b>openMSP430 Core top level directory</b></i></td></tr>
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<tbody><tr><td colspan="5"><b>core</b></td> <td><i><b>openMSP430 Core top level directory</b></i></td></tr>
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<tr><td rowspan="80" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
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<tr><td rowspan="80" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
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<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i></td></tr>
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<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br>
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</td></tr>
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<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr>
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<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr>
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<tr><td colspan="2">ram.v</td> <td><i>RAM verilog model</i></td></tr>
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<tr><td colspan="2">ram.v</td> <td><i>RAM verilog model</i></td></tr>
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<tr><td colspan="2">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
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<tr><td colspan="2">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
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<tr><td colspan="2">dbg_uart_tasks.v</td> <td><i>UART tasks for the serial debug interface</i></td></tr>
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<tr><td colspan="2">dbg_uart_tasks.v</td> <td><i>UART tasks for the serial debug interface</i></td></tr>
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<tr><td colspan="2">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
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<tr><td colspan="2">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
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<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
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<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
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<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr>
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<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr>
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<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
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<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
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<tr><td rowspan="22" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i></td></tr>
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<tr><td rowspan="22" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i><br>
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</td></tr>
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<tr><td rowspan="21" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration)</i></td></tr>
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<tr><td rowspan="21" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration)</i></td></tr>
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<tr><td colspan="2">openMSP430_undefines.v</td> <td><i>openMSP430 Verilog `undef file</i></td></tr>
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<tr><td colspan="2">openMSP430_undefines.v</td> <td><i>openMSP430 Verilog `undef file</i></td></tr>
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<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr>
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<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr>
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<tr><td colspan="2">omsp_frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
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<tr><td colspan="2">omsp_frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
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<tr><td colspan="2">omsp_execution_unit.v</td> <td><i>Execution unit</i></td></tr>
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<tr><td colspan="2">omsp_execution_unit.v</td> <td><i>Execution unit</i></td></tr>
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<tr><td colspan="2">synthesis.tcl</td> <td><i>Main synthesis TCL script</i></td></tr>
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<tr><td colspan="2">synthesis.tcl</td> <td><i>Main synthesis TCL script</i></td></tr>
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<tr><td colspan="2">library.tcl</td> <td><i>Load library, set operating conditions and wire load models</i></td></tr>
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<tr><td colspan="2">library.tcl</td> <td><i>Load library, set operating conditions and wire load models</i></td></tr>
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<tr><td colspan="2">read.tcl</td> <td><i>Read RTL</i></td></tr>
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<tr><td colspan="2">read.tcl</td> <td><i>Read RTL</i></td></tr>
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<tr><td colspan="2">constraints.tcl</td> <td><i>Set design constrains</i></td></tr>
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<tr><td colspan="2">constraints.tcl</td> <td><i>Set design constrains</i></td></tr>
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<tr><td colspan="2"><b>results</b></td> <td><i>Results directory</i></td></tr>
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<tr><td colspan="2"><b>results</b></td> <td><i>Results directory</i></td></tr>
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<tr><td colspan="3"><b>actel</b></td> <td><i>Actel synthesis setup for area & speed analysis</i></td></tr>
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<tr><td colspan="3"><b>actel</b></td> <td><i>Actel synthesis setup for area & speed analysis</i></td></tr>
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<tr><td colspan="3"><b>altera</b></td> <td><i>Altera synthesis setup for area & speed analysis</i></td></tr>
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<tr><td colspan="3"><b>altera</b></td> <td><i>Altera synthesis setup for area & speed analysis</i></td></tr>
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<tr><td colspan="3"><b>xilinx</b></td> <td><i>Xilinx synthesis setup for area & speed analysis</i></td></tr>
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<tr><td colspan="3"><b>xilinx</b></td> <td><i>Xilinx synthesis setup for area & speed analysis</i></td></tr>
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</table>
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</tbody></table>
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<br />
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<br>
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<a name="3. Directory structure: FGPA projects"></a>
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<a name="3. Directory structure: FGPA projects"></a>
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<div style="text-align: right"><a href="#TOC">Top</a></div>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>3. Directory structure: FGPA projects</h1>
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<h1>3. Directory structure: FGPA projects</h1>
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<a name="3.1 Xilinx Spartan 3 example"></a>
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<a name="3.1 Xilinx Spartan 3 example"></a>
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<h2>3.1 Xilinx Spartan 3 example</h2>
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<h2>3.1 Xilinx Spartan 3 example</h2>
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<table border="1">
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<table border="1">
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<tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
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<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
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<tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr>
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<tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr>
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<tr><td rowspan="51" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
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<tr><td rowspan="51" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
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<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i></td></tr>
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<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br>
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</td></tr>
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<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
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<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
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<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
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<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
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<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
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<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
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<tr><td colspan="3">glbl.v</td> <td><i>Xilinx "glbl.v" file</i></td></tr>
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<tr><td colspan="3">glbl.v</td> <td><i>Xilinx "glbl.v" file</i></td></tr>
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<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
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<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
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<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">board_user_guide.pdf</td> <td><i>Spartan-3 FPGA Starter Kit Board User Guide</i></td></tr>
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<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">board_user_guide.pdf</td> <td><i>Spartan-3 FPGA Starter Kit Board User Guide</i></td></tr>
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<tr><td colspan="4">msp430f1121a.pdf</td> <td><i>msp430f1121a Specification</i></td></tr>
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<tr><td colspan="4">msp430f1121a.pdf</td> <td><i>msp430f1121a Specification</i></td></tr>
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<tr><td colspan="4">xapp462.pdf</td> <td><i>Xilinx Digital Clock Managers (DCMs) user guide</i></td></tr>
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<tr><td colspan="4">xapp462.pdf</td> <td><i>Xilinx Digital Clock Managers (DCMs) user guide</i></td></tr>
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<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
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<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
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<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i></td></tr>
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<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i><br>
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</td></tr>
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<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
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<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
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<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
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<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
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<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
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<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
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<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
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<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
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<tr><td colspan="3"><b>coregen</b></td> <td><i>Xilinx's coregen directory</i></td></tr>
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<tr><td colspan="3"><b>coregen</b></td> <td><i>Xilinx's coregen directory</i></td></tr>
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<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
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<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
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<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
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<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
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<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
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<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
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<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
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<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
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<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>leds</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
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<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>leds</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
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<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">makefile</td> <td><i></i></td></tr>
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<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">makefile</td> <td><i></i><br>
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<tr><td colspan="3">hardware.h</td> <td><i></i></td></tr>
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</td></tr>
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<tr><td colspan="3">main.c</td> <td><i></i></td></tr>
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<tr><td colspan="3">hardware.h</td> <td><i></i><br>
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<tr><td colspan="3">7seg.h</td> <td><i></i></td></tr>
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</td></tr>
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<tr><td colspan="3">7seg.c</td> <td><i></i></td></tr>
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<tr><td colspan="3">main.c</td> <td><i></i><br>
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</td></tr>
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<tr><td colspan="3">7seg.h</td> <td><i></i><br>
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</td></tr>
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<tr><td colspan="3">7seg.c</td> <td><i></i><br>
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</td></tr>
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<tr><td colspan="4"><b>ta_uart</b></td> <td><i>Software UART with Timer_A (from the CDK4MSP project)</i></td></tr>
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<tr><td colspan="4"><b>ta_uart</b></td> <td><i>Software UART with Timer_A (from the CDK4MSP project)</i></td></tr>
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<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
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<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
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<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td> <td><i></i></td></tr>
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<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td> <td><i></i><br>
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</td></tr>
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<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">create_bitstream.sh</td> <td><i>Run Xilinx ISE synthesis in a Linux environment</i></td></tr>
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<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">create_bitstream.sh</td> <td><i>Run Xilinx ISE synthesis in a Linux environment</i></td></tr>
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<tr><td colspan="3">create_bitstream.bat</td> <td><i>Run Xilinx ISE synthesis in a Windows environment</i></td></tr>
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<tr><td colspan="3">create_bitstream.bat</td> <td><i>Run Xilinx ISE synthesis in a Windows environment</i></td></tr>
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<tr><td colspan="3">openMSP430_fpga.ucf</td> <td><i>UCF file</i></td></tr>
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<tr><td colspan="3">openMSP430_fpga.ucf</td> <td><i>UCF file</i></td></tr>
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<tr><td colspan="3">openMSP430_fpga.prj</td> <td><i>RTL file list to be synthesized</i></td></tr>
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<tr><td colspan="3">openMSP430_fpga.prj</td> <td><i>RTL file list to be synthesized</i></td></tr>
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<tr><td colspan="3">xst_verilog.opt</td> <td><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td></tr>
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<tr><td colspan="3">xst_verilog.opt</td> <td><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td></tr>
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<tr><td colspan="3">load_rom.sh</td> <td><i>Update bitstream's program memory with a given software ELF file in a Linux environment</i></td></tr>
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<tr><td colspan="3">load_rom.sh</td> <td><i>Update bitstream's program memory with a given software ELF file in a Linux environment</i></td></tr>
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<tr><td colspan="3">load_rom.bat</td> <td><i>Update bitstream's program memory with a given software ELF file in a Windows environment</i></td></tr>
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<tr><td colspan="3">load_rom.bat</td> <td><i>Update bitstream's program memory with a given software ELF file in a Windows environment</i></td></tr>
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<tr><td colspan="3">memory.bmm</td> <td><i>FPGA memory description for bitstream's program memory update</i></td></tr>
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<tr><td colspan="3">memory.bmm</td> <td><i>FPGA memory description for bitstream's program memory update</i></td></tr>
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</table>
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</tbody></table>
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<br />
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<br>
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<a name="3.2 Altera Cyclone II example"></a>
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<a name="3.2 Altera Cyclone II example"></a>
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<div style="text-align: right"><a href="#TOC">Top</a></div>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h2>3.2 Altera Cyclone II example</h2>
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<h2>3.2 Altera Cyclone II example</h2>
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<table border="1">
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<table border="1">
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<tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
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<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
|
<tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>altera_de1_board</b></td> <td><i><b>Altera FPGA Project based on Cyclone II Starter Development Board</b></i></td></tr>
|
<tr><td rowspan="49" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>altera_de1_board</b></td> <td><i><b>Altera FPGA Project based on Cyclone II Starter Development Board</b></i></td></tr>
|
<tr><td rowspan="48" valign="bottom"><font color="white">abcd</font></td> <td colspan="5">README</td> <td><i>README file</i></td></tr>
|
<tr><td rowspan="48" valign="bottom"><font color="white">abcd</font></td> <td colspan="5">README</td> <td><i>README file</i></td></tr>
|
<tr><td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
<tr><td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i></td></tr>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
|
</td></tr>
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
|
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
|
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
|
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
<tr><td colspan="3">altsyncram.v</td> <td><i>Altera verilog model of the altsyncram module.</i></td></tr>
|
<tr><td colspan="3">altsyncram.v</td> <td><i>Altera verilog model of the altsyncram module.</i></td></tr>
|
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
|
<tr><td colspan="5"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
|
<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">DE1_Board_Schematic.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Schematics</i></td></tr>
|
<tr><td rowspan="3"><font color="white">abcd</font></td> <td colspan="4">DE1_Board_Schematic.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Schematics</i></td></tr>
|
<tr><td colspan="4">DE1_Reference_Manual.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Reference Manual</i></td></tr>
|
<tr><td colspan="4">DE1_Reference_Manual.pdf</td> <td><i>Cyclone II FPGA Starter Development Board Reference Manual</i></td></tr>
|
<tr><td colspan="4">DE1_User_Guide.pdf</td> <td><i>Cyclone II FPGA Starter Development Board User Guide</i></td></tr>
|
<tr><td colspan="4">DE1_User_Guide.pdf</td> <td><i>Cyclone II FPGA Starter Development Board User Guide</i></td></tr>
|
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
|
<tr><td colspan="5"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
|
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i></td></tr>
|
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
|
</td></tr>
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">OpenMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">OpenMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
|
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
|
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
|
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
|
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
|
<tr><td colspan="3">ext_de1_sram.v</td> <td><i>Interface with altera DE1's external async SRAM (256kwords x 16bits)</i></td></tr>
|
<tr><td colspan="3">ext_de1_sram.v</td> <td><i>Interface with altera DE1's external async SRAM (256kwords x 16bits)</i></td></tr>
|
<tr><td colspan="3">ram16x512.v</td> <td><i>Single port RAM generated with the megafunction wizard</i></td></tr>
|
<tr><td colspan="3">ram16x512.v</td> <td><i>Single port RAM generated with the megafunction wizard</i></td></tr>
|
| Line 215... |
Line 224... |
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
|
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
|
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
|
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>bin</b></td> <td><i>Specific binaries required for software development.</i></td></tr>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>bin</b></td> <td><i>Specific binaries required for software development.</i></td></tr>
|
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">mifwrite.cpp</td> <td><i>This prog is taken from http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly changed to satisfy quartus6.1 *.mif eating engine.</i></td></tr>
|
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">mifwrite.cpp</td> <td><i>This
|
|
prog is taken from
|
|
http://www.johnloomis.org/ece595c/notes/isa/mifwrite.html and slightly
|
|
changed to satisfy quartus6.1 *.mif eating engine.</i></td></tr>
|
<tr><td colspan="3">mifwrite.exe</td> <td><i>Windows executable.</i></td></tr>
|
<tr><td colspan="3">mifwrite.exe</td> <td><i>Windows executable.</i></td></tr>
|
<tr><td colspan="3">mifwrite</td> <td><i>Linux executable.</i></td></tr>
|
<tr><td colspan="3">mifwrite</td> <td><i>Linux executable.</i></td></tr>
|
<tr><td colspan="4"><b>memledtest</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
|
<tr><td colspan="4"><b>memledtest</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
|
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>altera</b></td> <td><i></i></td></tr>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>altera</b></td> <td><i></i><br>
|
|
</td></tr>
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">main.qsf</td> <td><i>Global Assignments file</i></td></tr>
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">main.qsf</td> <td><i>Global Assignments file</i></td></tr>
|
<tr><td colspan="3">main.sof</td> <td><i>SOF file</i></td></tr>
|
<tr><td colspan="3">main.sof</td> <td><i>SOF file</i></td></tr>
|
<tr><td colspan="3">OpenMSP430_fpga.qpf</td> <td><i>Quartus II project file</i></td></tr>
|
<tr><td colspan="3">OpenMSP430_fpga.qpf</td> <td><i>Quartus II project file</i></td></tr>
|
<tr><td colspan="3">openMSP430_fpga_top.v</td> <td><i>RTL file list to be synthesized</i></td></tr>
|
<tr><td colspan="3">openMSP430_fpga_top.v</td> <td><i>RTL file list to be synthesized</i></td></tr>
|
</table>
|
</tbody></table>
|
<br />
|
<br>
|
|
|
|
<a name="3.3 Actel ProASIC3 example"></a>
|
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
|
<h2>3.3 Actel ProASIC3 example</h2>
|
|
|
|
<table border="1">
|
|
<tbody><tr><td colspan="6"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
|
|
<tr><td rowspan="43" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>actel_m1a3pl_dev_kit</b></td> <td><i><b>Actel FPGA Project based on the ProASIC3 M1A3PL development kit<br>
|
|
</b></i></td></tr>
|
|
|
|
<tr><td rowspan="42" style="vertical-align: top;"><font color="white">abcd</font></td>
|
|
<td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
|
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br>
|
|
</td></tr>
|
|
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">tb_openMSP430_fpga.v</td>
|
|
<td><i>FPGA testbench top level module</i></td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">registers.v</td>
|
|
<td><i>Connections to Core internals for easy debugging</i></td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td>
|
|
<td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">proasic3l.v</td>
|
|
<td><i>Actel ProASIC3L library file.<br>
|
|
</i></td></tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">DAC121S101.v<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><i>Verilog model of National's DAC121S101 12 bit DAC.</i></td>
|
|
</tr>
|
|
<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
|
|
<tr><td rowspan="2"><font color="white">abcd</font></td> <td colspan="3">M1A3PL_DEV_KIT_QS.pdf</td> <td><i>Development Kit Quickstart Card.</i></td></tr>
|
|
<tr><td colspan="3">M1IGLOO_StarterKit_v1_5_UG.pdf</td> <td><i>Development Kit User's Guide.</i></td></tr>
|
|
|
|
<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
|
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><br>
|
|
</td></tr>
|
|
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">openMSP430_fpga.v</td>
|
|
<td><i>FPGA top level file</i></td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">dac_spi_if.v</td>
|
|
<td><i>SPI interface to National's DAC121S101 12 bit DAC.<br>
|
|
</i></td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">smartgen</span><br>
|
|
</td>
|
|
<td><i>Actel's smartgen directory.</i></td></tr>
|
|
|
|
<tr><td style="vertical-align: top;"><font color="white">abcd</font></td>
|
|
<td colspan="1">dmem_128B.v</td> <td><i>128 Byte RAM (for data memory).<br>
|
|
</i></td></tr>
|
|
<tr><td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td colspan="1">pmem_2kB.v</td> <td><i>2 kByte RAM (for program memory).<br>
|
|
</i></td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>openmsp430</b></td>
|
|
<td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
|
|
<tr><td colspan="4"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
|
|
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
|
|
|
|
|
|
|
|
<tr> <td rowspan="10" style="vertical-align: top;"><br>
|
|
</td>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">bin</span><br>
|
|
</td>
|
|
<td style="font-style: italic;"><span style="font-weight: bold;">RTL simulation scripts</span><br>
|
|
</td></tr>
|
|
<tr>
|
|
<td colspan="1" rowspan="3" style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">msp430sim<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Main simulation script<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">ihex2mem.tcl<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Verilog program memory file generation<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">rtlsim.sh<br>
|
|
</td>
|
|
<td style="vertical-align: top;">Verilog Icarus simulation script<br>
|
|
</td>
|
|
</tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>run</b></td>
|
|
<td><i><b>For running RTL simulations</b></i></td></tr>
|
|
|
|
<tr> <td colspan="1" rowspan="2" style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">run<br>
|
|
</td>
|
|
<td><i>Run simulation of a given software project<br>
|
|
</i></td></tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">run_disassemble<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><i>Disassemble the program memory content of the latest simulation</i></td>
|
|
</tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;"><b>src</b></td>
|
|
<td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
|
|
|
<tr>
|
|
<td colspan="1" rowspan="2" style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">submit.f<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">Verilog simulator command file</span><br>
|
|
</td>
|
|
</tr>
|
|
<tr> <td style="vertical-align: top;">*.v<br>
|
|
</td>
|
|
<td><i>Stimulus vector for the corresponding software project</i></td></tr>
|
|
<tr><td colspan="4"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
|
|
|
|
|
|
|
|
|
<tr><td colspan="1" rowspan="2" style="vertical-align: top;"><br>
|
|
</td>
|
|
<td colspan="3"><span style="font-weight: bold;">spacewar</span><br>
|
|
</td> <td><span style="font-style: italic;">SpaceWar oscilloscope game.</span><br>
|
|
</td></tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td colspan="3" rowspan="1" style="vertical-align: top; text-align: center;"><img src="usercontent,img,1299013492" alt="Spacewar" title="Spacewar" width="25%"/><br>
|
|
</td>
|
|
</tr>
|
|
<tr><td colspan="4"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
|
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>actel</b></td> <td><br>
|
|
</td></tr>
|
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="2" rowspan="1" style="vertical-align: top;">prepare_implementation.tcl<br>
|
|
</td>
|
|
<td style="font-style: italic;">Generate required files prior synthesis and P&R.<br>
|
|
</td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">synplify.tcl<br>
|
|
</td>
|
|
<td style="font-style: italic;">Synplify template for the synthesis run.<br>
|
|
</td></tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">libero_designer.tcl<br>
|
|
</td>
|
|
<td style="font-style: italic;">Libero Designer template for the P&R run.<br>
|
|
</td></tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">design_files.v<br>
|
|
</td>
|
|
<td style="vertical-align: top; font-style: italic;">RTL file list to be synthesized.<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.pre.sdc<br>
|
|
</td>
|
|
<td style="vertical-align: top; font-style: italic;">Synthesis timing constraints.<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.post.sdc<br>
|
|
</td>
|
|
<td style="vertical-align: top; font-style: italic;">P&R timing constraints.<br>
|
|
</td>
|
|
</tr>
|
|
<tr><td colspan="2" rowspan="1" style="vertical-align: top;">design_constraints.pdc<br>
|
|
</td>
|
|
<td style="font-style: italic;">P&R physical constraints.<br>
|
|
</td></tr>
|
|
</tbody></table>
|
|
|
|
<br>
|
<a name="4. Directory structure: Software Development Tools"></a>
|
<a name="4. Directory structure: Software Development Tools"></a>
|
<div style="text-align: right"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>4. Directory structure: Software Development Tools</h1>
|
<h1>4. Directory structure: Software Development Tools</h1>
|
|
|
<table border="1">
|
<table border="1">
|
<tr><td colspan="5"><b>tools</b></td> <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr>
|
<tbody><tr><td colspan="5"><b>tools</b></td> <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr>
|
<tr><td rowspan="72" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bin</b></td> <td><i><b>Contains the executable files</b></i></td></tr>
|
<tr><td rowspan="72" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bin</b></td> <td><i><b>Contains the executable files</b></i></td></tr>
|
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openmsp430-loader.tcl</td> <td><i>Simple command line boot loader: TCL Script</i></td></tr>
|
<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openmsp430-loader.tcl</td> <td><i>Simple command line boot loader: TCL Script</i></td></tr>
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<tr><td colspan="3">openmsp430-loader.exe</td> <td><i>Simple command line boot loader: Windows executable</i></td></tr>
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<tr><td colspan="3">openmsp430-loader.exe</td> <td><i>Simple command line boot loader: Windows executable</i></td></tr>
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<tr><td colspan="3">openmsp430-minidebug.tcl</td> <td><i>Minimalistic debugger with simple GUI: TCL Script</i></td></tr>
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<tr><td colspan="3">openmsp430-minidebug.tcl</td> <td><i>Minimalistic debugger with simple GUI: TCL Script</i></td></tr>
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<tr><td colspan="3">openmsp430-minidebug.exe</td> <td><i>Minimalistic debugger with simple GUI: Windows executable</i></td></tr>
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<tr><td colspan="3">openmsp430-minidebug.exe</td> <td><i>Minimalistic debugger with simple GUI: Windows executable</i></td></tr>
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<tr><td colspan="4"><b>freewrap642</b></td> <td><i><b>The freeWrap program turns TCL/TK scripts into single-file binary executable programs for Windows.</b></i></td></tr>
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<tr><td colspan="4"><b>freewrap642</b></td> <td><i><b>The freeWrap program turns TCL/TK scripts into single-file binary executable programs for Windows.</b></i></td></tr>
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<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">freewrap.exe</td> <td><i>freeWrap executable to run on TCL/TK scripts (i.e. with GUI)</i></td></tr>
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<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">freewrap.exe</td> <td><i>freeWrap executable to run on TCL/TK scripts (i.e. with GUI)</i></td></tr>
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<tr><td colspan="3">freewrapTCLSH.exe</td> <td><i>freeWrap executable to run on pure TCL scripts (i.e. command line)</i></td></tr>
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<tr><td colspan="3">freewrapTCLSH.exe</td> <td><i>freeWrap executable to run on pure TCL scripts (i.e. command line)</i></td></tr>
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<tr><td colspan="3">tclpip85s.dll</td> <td><i>freeWrap mandatory DLL</i></td></tr>
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<tr><td colspan="3">tclpip85s.dll</td> <td><i>freeWrap mandatory DLL</i></td></tr>
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<tr><td colspan="3">generate_exec.bat</td> <td><i>Simple Batch file for auto generation of the tools' windows executables</i></td></tr>
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<tr><td colspan="3">generate_exec.bat</td> <td><i>Simple Batch file for auto generation of the tools' windows executables</i></td></tr>
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