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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<div style="text-align: right;"><a href="#TOC">Top</a></div>
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<h1>2. Directory structure: openMSP430 core</h1>
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<h1>2. Directory structure: openMSP430 core</h1>
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<table border="1">
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<table border="1">
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<tbody><tr><td colspan="5"><b>core</b></td> <td><i><b>openMSP430 Core top level directory</b></i></td></tr>
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<tbody><tr><td colspan="5"><b>core</b></td> <td><i><b>openMSP430 Core top level directory</b></i></td></tr>
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<tr><td rowspan="107" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
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<tr><td rowspan="120" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
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<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br>
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<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>verilog</b></td> <td><i></i><br>
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</td></tr>
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</td></tr>
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<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr>
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<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">tb_openMSP430.v</td> <td><i>Testbench top level module</i></td></tr>
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<tr><td colspan="2">ram.v</td> <td><i>RAM verilog model</i></td></tr>
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<tr><td colspan="2">ram.v</td> <td><i>RAM verilog model</i></td></tr>
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<tr><td colspan="2">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
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<tr><td colspan="2">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
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<tr><td colspan="2">dbg_uart_tasks.v</td> <td><i>UART tasks for the serial debug interface</i></td></tr>
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<tr><td colspan="2">dbg_uart_tasks.v</td> <td><i>UART tasks for the serial debug interface</i></td></tr>
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<tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;">dbg_i2c_tasks.v<br>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">I2C tasks for the serial debug interface</span><br>
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</td>
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</tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;">io_cell.v<br>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">Generic I/O cell model for building the serial debug interface I2C bus</span><br>
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</td>
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</tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td>
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<td colspan="2" rowspan="1" style="vertical-align: top;">msp_debug.v</td>
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<td style="vertical-align: top;"><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td>
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<td style="vertical-align: top;"><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td>
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</tr>
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</tr>
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<tr><td colspan="2">timescale.v</td> <td><i>Global time scale definition for simulation.</i></td></tr>
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<tr><td colspan="2">timescale.v</td> <td><i>Global time scale definition for simulation.</i></td></tr>
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<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
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<tr><td colspan="4"><b>doc</b></td> <td><i><b>Diverse documentation</b></i></td></tr>
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<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr>
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<tr><td><font color="white">abcd</font></td> <td colspan="3">slau049f.pdf</td> <td><i>MSP430x1xx Family User's Guide</i></td></tr>
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<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
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<tr><td colspan="4"><b>rtl</b></td> <td><i><b>RTL sources</b></i></td></tr>
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<tr><td rowspan="30" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i><br>
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<tr><td rowspan="31" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>verilog</b></td> <td><i></i><br>
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</td></tr>
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</td></tr>
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<tr><td rowspan="29" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration, ...)</i></td></tr>
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<tr><td rowspan="30" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">openMSP430_defines.v</td> <td><i>openMSP430 core configuration file (Program and Data memory size definition, Debug Interface configuration, ...)</i></td></tr>
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<tr><td colspan="2">openMSP430_undefines.v</td> <td><i>openMSP430 Verilog `undef file</i></td></tr>
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<tr><td colspan="2">openMSP430_undefines.v</td> <td><i>openMSP430 Verilog `undef file</i></td></tr>
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<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr>
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<tr><td colspan="2">openMSP430.v</td> <td><i>openMSP430 top level</i></td></tr>
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<tr><td colspan="2">omsp_frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
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<tr><td colspan="2">omsp_frontend.v</td> <td><i>Instruction fetch and decode</i></td></tr>
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<tr><td colspan="2">omsp_execution_unit.v</td> <td><i>Execution unit</i></td></tr>
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<tr><td colspan="2">omsp_execution_unit.v</td> <td><i>Execution unit</i></td></tr>
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<tr><td colspan="2">omsp_alu.v</td> <td><i>ALU</i></td></tr>
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<tr><td colspan="2">omsp_alu.v</td> <td><i>ALU</i></td></tr>
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<tr><td colspan="2">omsp_multiplier.v</td> <td><i>16x16 Hardware Multiplier</i></td></tr>
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<tr><td colspan="2">omsp_multiplier.v</td> <td><i>16x16 Hardware Multiplier</i></td></tr>
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<tr><td colspan="2">omsp_dbg.v</td> <td><i>Serial Debug Interface main block</i></td></tr>
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<tr><td colspan="2">omsp_dbg.v</td> <td><i>Serial Debug Interface main block</i></td></tr>
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<tr><td colspan="2">omsp_dbg_hwbrk.v</td> <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr>
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<tr><td colspan="2">omsp_dbg_hwbrk.v</td> <td><i>Serial Debug Interface hardware breakpoint unit</i></td></tr>
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<tr><td colspan="2">omsp_dbg_uart.v</td> <td><i>Serial Debug Interface UART communication block</i></td></tr>
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<tr><td colspan="2">omsp_dbg_uart.v</td> <td><i>Serial Debug Interface UART communication block</i></td></tr>
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<tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;">omsp_dbg_i2c.v<br>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">Serial Debug Interface I2C communication block</span><br>
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</td>
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</tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;">omsp_sync_cell.v</td>
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<td colspan="2" rowspan="1" style="vertical-align: top;">omsp_sync_cell.v</td>
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<td style="vertical-align: top;"><i>Simple synchronization module (double flip-flop).</i></td>
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<td style="vertical-align: top;"><i>Simple synchronization module (double flip-flop).</i></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;">omsp_sync_reset.v</td>
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<td colspan="2" rowspan="1" style="vertical-align: top;">omsp_sync_reset.v</td>
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</tr>
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</tr>
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<tr><td colspan="1">omsp_timerA.v</td> <td><i>Timer A</i></td></tr>
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<tr><td colspan="1">omsp_timerA.v</td> <td><i>Timer A</i></td></tr>
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<tr><td colspan="1">template_periph_16b.v</td> <td><i>Verilog template for 16 bit peripherals</i></td></tr>
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<tr><td colspan="1">template_periph_16b.v</td> <td><i>Verilog template for 16 bit peripherals</i></td></tr>
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<tr><td colspan="1">template_periph_8b.v</td> <td><i>Verilog template for 8 bit peripherals</i></td></tr>
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<tr><td colspan="1">template_periph_8b.v</td> <td><i>Verilog template for 8 bit peripherals</i></td></tr>
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<tr><td colspan="4"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
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<tr><td colspan="4"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
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<tr><td rowspan="54" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
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<tr><td colspan="1" rowspan="62" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
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<tr><td rowspan="53" valign="bottom"><font color="white">abcd</font></td> <td colspan="2"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
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<tr><td colspan="1" rowspan="61" valign="bottom"><font color="white">abcd</font></td> <td colspan="2"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
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<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">msp430sim</td> <td><i>Main simulation script for assembler vector sources (located in the <span style="font-weight: bold;">src</span> directory)<br>
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<tr><td colspan="1" rowspan="10" valign="bottom"><font color="white">abcd</font><br>
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</td> <td colspan="1">msp430sim</td> <td><i>Main simulation script for assembler vector sources (located in the <span style="font-weight: bold;">src</span> directory)<br>
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</i></td></tr>
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</i></td></tr>
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<tr>
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<tr>
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<td style="vertical-align: top;">msp430sim_c<br>
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<td style="vertical-align: top;">msp430sim_c<br>
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</td>
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</td>
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<td style="vertical-align: top;"><i>Main simulation script for C vector sources</i><i> (located in the <span style="font-weight: bold;">src-c</span> directory)</i></td>
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<td style="vertical-align: top;"><i>Main simulation script for C vector sources</i><i> (located in the <span style="font-weight: bold;">src-c</span> directory)</i></td>
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<tr><td colspan="1">asm2ihex.sh</td> <td><i>Assembly file compilation (Intel HEX file generation)</i></td></tr>
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<tr><td colspan="1">asm2ihex.sh</td> <td><i>Assembly file compilation (Intel HEX file generation)</i></td></tr>
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<tr><td colspan="1">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
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<tr><td colspan="1">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
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<tr><td colspan="1">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
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<tr><td colspan="1">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
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<tr><td colspan="1">template.x</td> <td><i>ASM linker definition file template</i></td></tr>
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<tr><td colspan="1">template.x</td> <td><i>ASM linker definition file template</i></td></tr>
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<tr>
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<tr>
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<td style="vertical-align: top;"><br>
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<td style="vertical-align: top;">template_defs.asm<br>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">Common ASM definition file included in all ".s43" files</span><br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">omsp_config.sh<br>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">oMSP configuration file.</span><br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">parse_results<br>
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</td>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">Script parsing regression log files and generating summary report.</span><br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">cov_*<br>
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<td style="vertical-align: top;">cov_*<br>
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</td>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">Code coverage scripts for NC-Verilog and ICM</span><br>
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<td style="vertical-align: top;"><span style="font-style: italic;">Code coverage scripts for NC-Verilog and ICM</span><br>
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</td>
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</td>
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</tr>
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</tr>
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</td>
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</td>
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<td style="vertical-align: top; font-style: italic;">Performs the coverage report merging of the regression run and starts ICM for the analysis.<br>
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<td style="vertical-align: top; font-style: italic;">Performs the coverage report merging of the regression run and starts ICM for the analysis.<br>
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</td>
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</td>
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</tr>
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</tr>
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<tr><td colspan="1">load_waveform.sav</td> <td><i>SAV file for gtkWave</i></td></tr>
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<tr><td colspan="1">load_waveform.sav</td> <td><i>SAV file for gtkWave</i></td></tr>
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<tr><td colspan="2"><b>src</b></td> <td><i><b>RTL simulation vectors sources</b></i></td></tr>
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<tr><td colspan="2"><b>src</b></td> <td><i><b>RTL simulation vectors sources (ASM based)<br>
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</b></i></td></tr>
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<tr><td rowspan="36" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">ldscript_example.x<br>
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<tr><td rowspan="36" valign="bottom"><font color="white">abcd</font></td> <td colspan="1">ldscript_example.x<br>
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</td> <td><i>MSPGCC toolchain linker script example</i></td></tr>
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</td> <td><i>MSPGCC toolchain linker script example</i></td></tr>
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<tr>
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<tr>
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<td style="vertical-align: top;">submit.prj<br>
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<td style="vertical-align: top;">submit.prj<br>
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</td>
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</td>
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| Line 229... |
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<tr>
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<tr>
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<td style="vertical-align: top;">scan.s43</td>
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<td style="vertical-align: top;">scan.s43</td>
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<td style="vertical-align: top;"><i>Scan test assembler vector files</i></td>
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<td style="vertical-align: top;"><i>Scan test assembler vector files</i></td>
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</tr>
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</tr>
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<tr><td colspan="1">scan.v</td> <td><i>Scan test verilog stimulus vector files</i></td></tr>
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<tr><td colspan="1">scan.v</td> <td><i>Scan test verilog stimulus vector files</i></td></tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">src-c</span><br>
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</td>
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<td style="vertical-align: top;"><i><b>RTL simulation vectors sources (C based)</b></i></td>
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</tr>
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<tr>
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<td colspan="1" rowspan="4" style="vertical-align: top;"><br>
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</td>
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<td style="vertical-align: top;">coremark_v1.0<br>
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</td>
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<td style="vertical-align: top; font-style: italic;">CoreMark benchmark<br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">dhrystone_v2.1<br>
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</td>
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<td style="vertical-align: top; font-style: italic;">Dhrystone benchmark ("official" version)<br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">dhrystone_4mcu<br>
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</td>
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<td style="vertical-align: top; font-style: italic;">Dhrystone benchmark (MCU adapted)<br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;">sandbox<br>
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</td>
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<td style="vertical-align: top; font-style: italic;">Small playground :-)<br>
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</td>
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</tr>
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<tr><td colspan="4"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
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<tr><td colspan="4"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
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<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>synopsys</b></td><td><i>Synopsys (Design Compiler) directory</i></td></tr>
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<tr><td rowspan="12" valign="bottom"><font color="white">abcd</font></td><td colspan="3"><b>synopsys</b></td><td><i>Synopsys (Design Compiler) directory</i></td></tr>
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<tr><td rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run_syn</td> <td><i>Run synthesis</i></td></tr>
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<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run_syn</td> <td><i>Run synthesis</i></td></tr>
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<tr>
|
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<td colspan="2" rowspan="1" style="vertical-align: top;">run_tmax<br>
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</td>
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<td style="vertical-align: top;"><span style="font-style: italic;">Run ATPG</span><br>
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</td>
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</tr>
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<tr><td colspan="2">synthesis.tcl</td> <td><i>Main synthesis TCL script</i></td></tr>
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<tr><td colspan="2">synthesis.tcl</td> <td><i>Main synthesis TCL script</i></td></tr>
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<tr><td colspan="2">library.tcl</td> <td><i>Load library, set operating conditions and wire load models</i></td></tr>
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<tr><td colspan="2">library.tcl</td> <td><i>Load library, set operating conditions and wire load models</i></td></tr>
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<tr><td colspan="2">read.tcl</td> <td><i>Read RTL</i></td></tr>
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<tr><td colspan="2">read.tcl</td> <td><i>Read RTL</i></td></tr>
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<tr><td colspan="2">constraints.tcl</td> <td><i>Set design constrains</i></td></tr>
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<tr><td colspan="2">constraints.tcl</td> <td><i>Set design constrains</i></td></tr>
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<tr>
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<td colspan="2" rowspan="1" style="vertical-align: top;">tmax.tcl<br>
|
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</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">Main TetraMax (ATPG) script.</span><br>
|
|
</td>
|
|
</tr>
|
<tr><td colspan="2"><b>results</b></td> <td><i>Results directory</i></td></tr>
|
<tr><td colspan="2"><b>results</b></td> <td><i>Results directory</i></td></tr>
|
<tr><td colspan="3"><b>actel</b></td> <td><i>Actel synthesis setup for area & speed analysis</i></td></tr>
|
<tr><td colspan="3"><b>actel</b></td> <td><i>Actel synthesis setup for area & speed analysis</i></td></tr>
|
<tr><td colspan="3"><b>altera</b></td> <td><i>Altera synthesis setup for area & speed analysis</i></td></tr>
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<tr><td colspan="3"><b>altera</b></td> <td><i>Altera synthesis setup for area & speed analysis</i></td></tr>
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<tr><td colspan="3"><b>xilinx</b></td> <td><i>Xilinx synthesis setup for area & speed analysis</i></td></tr>
|
<tr><td colspan="3"><b>xilinx</b></td> <td><i>Xilinx synthesis setup for area & speed analysis</i></td></tr>
|
</tbody></table>
|
</tbody></table>
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<a name="3.1 Xilinx Spartan 3 example"></a>
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<a name="3.1 Xilinx Spartan 3 example"></a>
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<h2>3.1 Xilinx Spartan 3 example</h2>
|
<h2>3.1 Xilinx Spartan 3 example</h2>
|
|
|
<table border="1">
|
<table border="1">
|
<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
|
<tbody><tr><td colspan="7"><b>fpga</b></td> <td><i><b>openMSP430 FPGA Projects top level directory</b></i></td></tr>
|
<tr><td rowspan="53" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr>
|
<tr><td rowspan="61" valign="bottom"><font color="white">abcd</font></td> <td colspan="6"><b>xilinx_diligent_s3_board</b></td> <td><i><b>Xilinx FPGA Project based on the Diligent Spartan-3 board</b></i></td></tr>
|
<tr><td rowspan="52" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
<tr><td rowspan="60" valign="bottom"><font color="white">abcd</font></td> <td colspan="5"><b>bench</b></td> <td><i><b>Top level testbench directory</b></i></td></tr>
|
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td colspan="4"><b>verilog</b></td> <td><i></i><br>
|
</td></tr>
|
</td></tr>
|
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
|
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">tb_openMSP430_fpga.v</td> <td><i>FPGA testbench top level module</i></td></tr>
|
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
|
<tr><td colspan="3">registers.v</td> <td><i>Connections to Core internals for easy debugging</i></td></tr>
|
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
<tr><td colspan="3">msp_debug.v</td> <td><i>Testbench instruction decoder and ASCII chain generator for easy debugging</i></td></tr>
|
| Line 275... |
Line 356... |
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
|
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">openMSP430_fpga.v</td> <td><i>FPGA top level file</i></td></tr>
|
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
|
<tr><td colspan="3">driver_7segment.v</td> <td><i>Four-Digit, Seven-Segment LED Display driver</i></td></tr>
|
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
|
<tr><td colspan="3">io_mux.v</td> <td><i>I/O mux for port function selection.</i></td></tr>
|
<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
|
<tr><td colspan="3"><b>openmsp430</b></td> <td><i><b>Local copy of the openMSP430 core.</b> The *define.v file has been adjusted to the requirements of the project.</i></td></tr>
|
<tr><td colspan="3"><b>coregen</b></td> <td><i>Xilinx's coregen directory</i></td></tr>
|
<tr><td colspan="3"><b>coregen</b></td> <td><i>Xilinx's coregen directory</i></td></tr>
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">ram_8x512_hi.*</td> <td><i>512 Byte RAM (upper byte)</i></td></tr>
|
<tr><td rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="2">ram_8x512_hi.*<i><br>
|
<tr><td colspan="2">ram_8x512_lo.*</td> <td><i>512 Byte RAM (lower byte)</i></td></tr>
|
</i></td> <td style="vertical-align: top;"><i>512 Byte RAM (upper byte)</i></td>
|
<tr><td colspan="2">ram_8x2k_hi.*</td> <td><i>2 kByte RAM (upper byte)</i></td></tr>
|
</tr>
|
<tr><td colspan="2">ram_8x2k_lo.*</td> <td><i>2 kByte RAM (lower byte)</i></td></tr>
|
<tr><td rowspan="1" colspan="2">ram_8x512_lo.*<i><br>
|
|
</i></td> <td style="vertical-align: top;"><i>512 Byte RAM (lower byte)</i></td>
|
|
</tr>
|
|
<tr><td rowspan="1" colspan="2">ram_8x2k_hi.*<i><br>
|
|
</i></td> <td style="vertical-align: top;"><i>2 kByte RAM (upper byte)</i></td>
|
|
</tr>
|
|
<tr><td rowspan="1" colspan="2">ram_8x2k_lo.*<i><br>
|
|
</i></td> <td style="vertical-align: top;"><i>2 kByte RAM (lower byte)</i></td>
|
|
</tr>
|
<tr><td colspan="5"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
|
<tr><td colspan="5"><b>sim</b></td> <td><i><b>Top level simulations directory</b></i></td></tr>
|
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
|
<tr><td rowspan="11" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>rtl_sim</b></td> <td><i><b>RTL simulations</b></i></td></tr>
|
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
|
<tr><td rowspan="10" valign="bottom"><font color="white">abcd</font></td> <td colspan="3"><b>bin</b></td> <td><i><b>RTL simulation scripts</b></i></td></tr>
|
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">msp430sim</td> <td><i>Main simulation script</i></td></tr>
|
<tr><td rowspan="3" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="2">msp430sim<i><br>
|
<tr><td colspan="2">ihex2mem.tcl</td> <td><i>Verilog program memory file generation</i></td></tr>
|
</i></td> <td style="vertical-align: top;"><i>Main simulation script</i></td>
|
<tr><td colspan="2">rtlsim.sh</td> <td><i>Verilog Icarus simulation script</i></td></tr>
|
</tr>
|
|
<tr><td rowspan="1" colspan="2">ihex2mem.tcl<i><br>
|
|
</i></td> <td style="vertical-align: top;"><i>Verilog program memory file generation</i></td>
|
|
</tr>
|
|
<tr><td rowspan="1" colspan="2">rtlsim.sh<i><br>
|
|
</i></td> <td style="vertical-align: top;"><i>Verilog Icarus simulation script</i></td>
|
|
</tr>
|
<tr><td colspan="3"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
|
<tr><td colspan="3"><b>run</b></td> <td><i><b>For running RTL simulations</b></i></td></tr>
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">run</td> <td><i>Run simulation of a given software project</i></td></tr>
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="2">run<i><br>
|
<tr><td colspan="2">run_disassemble</td> <td><i>Disassemble the program memory content of the latest simulation</i></td></tr>
|
</i></td> <td style="vertical-align: top;"><i>Run simulation of a given software project</i></td>
|
|
</tr>
|
|
<tr><td rowspan="1" colspan="2">run_disassemble<i><br>
|
|
</i></td> <td style="vertical-align: top;"><i>Disassemble the program memory content of the latest simulation</i></td>
|
|
</tr>
|
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
<tr><td colspan="3"><b>src</b></td> <td><i><b>RTL simulation verilog stimulus</b></i></td></tr>
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td colspan="2">submit.f</td> <td><i>Verilog simulator command file</i></td></tr>
|
<tr><td rowspan="2" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="2">submit.f<i><br>
|
<tr><td colspan="2">*.v</td> <td><i>Stimulus vector for the corresponding software project</i></td></tr>
|
</i></td> <td style="vertical-align: top;"><i>Verilog simulator command file</i></td>
|
|
</tr>
|
|
<tr><td colspan="1">*.v</td> <td><i><br>
|
|
</i></td><td style="vertical-align: top;"><i>Stimulus vector for the corresponding software project</i></td>
|
|
</tr>
|
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
<tr><td colspan="5"><b>software</b></td> <td><i><b>Software C programs to be loaded in the program memory</b></i></td></tr>
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>leds</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
|
<tr><td rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>leds</b></td> <td><i>LEDs blinking application (from the CDK4MSP project)</i></td></tr>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">makefile</td> <td><i></i><br>
|
<tr><td rowspan="5" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">makefile</td> <td><br>
|
</td></tr>
|
</td></tr>
|
<tr><td colspan="3">hardware.h</td> <td><i></i><br>
|
<tr><td colspan="3">hardware.h</td> <td><br>
|
</td></tr>
|
</td></tr>
|
<tr><td colspan="3">main.c</td> <td><i></i><br>
|
<tr><td colspan="3">main.c</td> <td><br>
|
</td></tr>
|
</td></tr>
|
<tr><td colspan="3">7seg.h</td> <td><i></i><br>
|
<tr><td colspan="3">7seg.h</td> <td><br>
|
</td></tr>
|
</td></tr>
|
<tr><td colspan="3">7seg.c</td> <td><i></i><br>
|
<tr><td colspan="3">7seg.c</td> <td><br>
|
</td></tr>
|
</td></tr>
|
<tr><td colspan="4"><b>ta_uart</b></td> <td><i>Software UART with Timer_A (from the CDK4MSP project)</i></td></tr>
|
<tr><td colspan="4"><b>ta_uart</b></td> <td><i>Software UART with Timer_A (from the CDK4MSP project)</i></td></tr>
|
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
<tr><td colspan="5"><b>synthesis</b></td> <td><i><b>Top level synthesis directory</b></i></td></tr>
|
<tr><td rowspan="9" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td> <td><i></i><br>
|
<tr><td rowspan="17" valign="bottom"><font color="white">abcd</font></td><td colspan="4"><b>xilinx</b></td> <td><br>
|
</td></tr>
|
</td></tr>
|
<tr><td rowspan="8" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">create_bitstream.sh</td> <td><i>Run Xilinx ISE synthesis in a Linux environment</i></td></tr>
|
<tr><td rowspan="16" valign="bottom"><font color="white">abcd</font></td> <td colspan="3">0_create_bitstream.sh</td> <td><i>Run Xilinx ISE synthesis in a Linux environment</i></td></tr>
|
<tr><td colspan="3">create_bitstream.bat</td> <td><i>Run Xilinx ISE synthesis in a Windows environment</i></td></tr>
|
<tr><td colspan="3">1_initialize_pmem.sh<br>
|
<tr><td colspan="3">openMSP430_fpga.ucf</td> <td><i>UCF file</i></td></tr>
|
</td> <td><i>Update bitstream's program memory with a given software ELF file<br>
|
<tr><td colspan="3">openMSP430_fpga.prj</td> <td><i>RTL file list to be synthesized</i></td></tr>
|
</i></td></tr>
|
<tr><td colspan="3">xst_verilog.opt</td> <td><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td></tr>
|
<tr>
|
<tr><td colspan="3">load_rom.sh</td> <td><i>Update bitstream's program memory with a given software ELF file in a Linux environment</i></td></tr>
|
<td colspan="3" rowspan="1" style="vertical-align: top;">2_generate_prom_file.sh<br>
|
<tr><td colspan="3">load_rom.bat</td> <td><i>Update bitstream's program memory with a given software ELF file in a Windows environment</i></td></tr>
|
</td>
|
<tr><td colspan="3">memory.bmm</td> <td><i>FPGA memory description for bitstream's program memory update</i></td></tr>
|
<td style="vertical-align: top;"><span style="font-style: italic;">Generate PROM file</span><br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;">3_program_fpga.sh<br>
|
|
</td>
|
|
<td style="vertical-align: top; font-style: italic;">Program FPGA and on-board flash memory<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="3" rowspan="1" style="vertical-align: top;"><span style="font-weight: bold;">bitstreams</span><br>
|
|
</td>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="1" rowspan="3" style="vertical-align: top;"><br>
|
|
</td>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">*.bit<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">Bitstream files</span><br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">*.mcs<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">PROM files</span><br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">README.jpg<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">README file</span><br>
|
|
</td>
|
|
</tr>
|
|
<tr><td colspan="3"><span style="font-weight: bold;">scripts</span><br>
|
|
</td> <td><i><br>
|
|
</i></td></tr>
|
|
<tr>
|
|
<td colspan="1" rowspan="7" style="vertical-align: top;"><br>
|
|
</td>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">ihex2mem.tcl<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">TCL script converting Intel-HEX format to Verilog memory file.</span><br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">impact_generate<br>
|
|
_prom_file.batch<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">iMPACT TCL script for PROM file generation.</span><br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">impact_program<br>
|
|
_fpga.batch<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><span style="font-style: italic;">iMPACT TCL script for programing the FPGA and on-board flash memory.</span></td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">memory.bmm<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><i>FPGA memory description for bitstream's program memory update</i></td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">openMSP430_fpga.ucf</td>
|
|
<td style="vertical-align: top;"><i>UCF file</i></td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">openMSP430_fpga.prj</td>
|
|
<td style="vertical-align: top;"><i>RTL file list to be synthesized</i></td>
|
|
</tr>
|
|
<tr>
|
|
<td colspan="2" rowspan="1" style="vertical-align: top;">xst_verilog.opt</td>
|
|
<td style="vertical-align: top;"><i>Verilog Option File for XST. Among other things, the search path to the include files is specified here.</i></td>
|
|
</tr>
|
|
|
|
|
|
|
|
|
|
|
</tbody></table>
|
</tbody></table>
|
<br>
|
<br>
|
|
|
<a name="3.2 Altera Cyclone II example"></a>
|
<a name="3.2 Altera Cyclone II example"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
| Line 569... |
Line 752... |
<h1>4. Directory structure: Software Development Tools</h1>
|
<h1>4. Directory structure: Software Development Tools</h1>
|
|
|
<table border="1">
|
<table border="1">
|
<tbody><tr><td colspan="4"><b>tools</b></td> <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr>
|
<tbody><tr><td colspan="4"><b>tools</b></td> <td><i><b>openMSP430 Software Development Tools top level directory</b></i></td></tr>
|
<tr>
|
<tr>
|
<td colspan="1" rowspan="19" style="vertical-align: top;"><font color="white">abcd</font></td>
|
<td colspan="1" rowspan="21" style="vertical-align: top;"><font color="white">abcd</font></td>
|
<td colspan="3" rowspan="1" style="vertical-align: top;">omsp_alias.xml<br>
|
<td colspan="3" rowspan="1" style="vertical-align: top;">omsp_alias.xml<br>
|
</td>
|
</td>
|
<td style="vertical-align: top;"><span style="font-style: italic;">This
|
<td style="vertical-align: top;"><span style="font-style: italic;">This
|
XML file allows the software development tools to identify a openMSP430
|
XML file allows the software development tools to identify a openMSP430
|
implementation, and add customized extra information (Alias, URL, ...).</span><br>
|
implementation, and add customized extra information (Alias, URL, ...).</span><br>
|
| Line 588... |
Line 771... |
<tr><td colspan="2">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends<br>
|
<tr><td colspan="2">openmsp430-gdbproxy.tcl</td> <td><i>GDB Proxy server to be used together with MSP430-GDB and the Eclipse, DDD, or Insight graphical front-ends<br>
|
</i></td></tr>
|
</i></td></tr>
|
<tr><td colspan="2">README.TXT</td> <td><i>README file regarding the use of TCL scripts in a Windows environment.</i></td></tr>
|
<tr><td colspan="2">README.TXT</td> <td><i>README file regarding the use of TCL scripts in a Windows environment.</i></td></tr>
|
|
|
<tr><td colspan="3"><b>lib</b></td> <td><i><b>Common library</b></i></td></tr>
|
<tr><td colspan="3"><b>lib</b></td> <td><i><b>Common library</b></i></td></tr>
|
<tr><td colspan="1" rowspan="5" valign="bottom"><font color="white">abcd</font></td><td colspan="2"><b>tcl-lib</b></td> <td><i><b>Common TCL library</b></i></td></tr>
|
<tr><td colspan="1" rowspan="7" valign="bottom"><font color="white">abcd</font></td><td colspan="2"><b>tcl-lib</b></td> <td><i><b>Common TCL library</b></i></td></tr>
|
<tr><td colspan="1" rowspan="4" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="1">dbg_uart.tcl<i><br>
|
<tr><td colspan="1" rowspan="6" valign="bottom"><font color="white">abcd</font></td> <td rowspan="1" colspan="1">dbg_uart_generic.tcl<i><br>
|
</i></td> <td style="vertical-align: top;"><i>Low level UART communication functions</i></td>
|
</i></td> <td style="vertical-align: top;"><i>Low level Generic UART communication functions</i></td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">dbg_i2c_usb-iss.tcl<br>
|
|
</td>
|
|
<td style="vertical-align: top;"><i>Low level I2C communication functions for the USB-ISS adapter<br>
|
|
</i></td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;">dbg_utils.tcl</td>
|
|
<td style="vertical-align: top;"><i>Low level "COMx:" "/dev/tty" communication functions</i></td>
|
</tr>
|
</tr>
|
<tr><td rowspan="1" colspan="1">dbg_functions.tcl<i><br>
|
<tr><td rowspan="1" colspan="1">dbg_functions.tcl<i><br>
|
</i></td> <td style="vertical-align: top;"><i>Main utility functions for the openMSP430 serial debug interface</i></td>
|
</i></td> <td style="vertical-align: top;"><i>Main utility functions for the openMSP430 serial debug interface</i></td>
|
</tr>
|
</tr>
|
<tr><td rowspan="1" colspan="1">combobox.tcl<i><br>
|
<tr><td rowspan="1" colspan="1">combobox.tcl<i><br>
|
