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<h1>1. Overview</h1>
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<h1>1. Overview</h1>
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This chapter aims to give a comprehensive description of all openMSP430 core interfaces in order to facilitates its integration within an ASIC or FPGA.<br /><br />
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This chapter aims to give a comprehensive description of all openMSP430 core interfaces in order to facilitates its integration within an ASIC or FPGA.<br /><br />
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The following diagram shows an overview of the openMSP430 core connectivity:<br /><br />
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The following diagram shows an overview of the openMSP430 core connectivity:<br /><br />
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<img src="getimg.php?1264010073" width="100%" alt="Core Integration - 23 Jan 2010" title="Core Integration - 23 Jan 2010" />
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<img src="usercontent,img,1306268589" width="100%" alt="Core Integration - 24 May 2011" title="Core Integration - 24 May 2011" />
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<br /><br />
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<br /><br />
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The full pinout of the core is summarized in the following table.<br />
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The full pinout of the core is summarized in the following table.<br />
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<br />
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<br />
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<table border="1">
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<table border="1">
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<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
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<tr> <td align="center"><b>Port Name</b></td> <td align="center"><b>Direction</b></td> <td align="center"><b>Width</b> </td> <td align="center"><b>Description</b></td> </tr>
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<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
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<tr> <td colspan="4" align="center"> <b><i>Clocks</i></b> </td></tr>
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<tr>
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<tr>
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<td> <a href="#2. Clocks">cpu_en</a> </td>
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<td> Input </td>
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<td> 1 </td>
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<td> Enable CPU code execution (asynchronous) </td>
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</tr>
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<tr>
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<td> <a href="#2. Clocks">dco_clk</a> </td>
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<td> <a href="#2. Clocks">dco_clk</a> </td>
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<td> Input </td>
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<td> Input </td>
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<td> 1 </td>
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<td> 1 </td>
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<td> Fast oscillator (fast clock), CPU clock </td>
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<td> Fast oscillator (fast clock), CPU clock </td>
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</tr>
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</tr>
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| Line 62... |
Line 68... |
<td> SMCLK enable </td>
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<td> SMCLK enable </td>
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</tr>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
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<tr> <td colspan="4" align="center"> <b><i>Resets</i></b> </td></tr>
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<tr>
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<tr>
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<td> <a href="#3. Resets">puc</a> </td>
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<td> <a href="#3. Resets">puc_rst</a> </td>
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<td> Output </td>
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<td> Output </td>
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<td> 1 </td>
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<td> 1 </td>
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<td> Main system reset </td>
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<td> Main system reset </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#3. Resets">reset_n</a> </td>
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<td> <a href="#3. Resets">reset_n</a> </td>
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<td> Input </td>
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<td> Input </td>
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<td> 1 </td>
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<td> 1 </td>
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<td> Reset Pin (low active) </td>
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<td> Reset Pin (low active, asynchronous) </td>
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</tr>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
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<tr> <td colspan="4" align="center"> <b><i>Program Memory interface</i></b> </td></tr>
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<tr>
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<tr>
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| Line 104... |
Line 110... |
</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#4. Program Memory">pmem_wen</a> </td>
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<td> <a href="#4. Program Memory">pmem_wen</a> </td>
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<td> Output </td>
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<td> Output </td>
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<td> 2 </td>
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<td> 2 </td>
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<td> Program Memory write enable (low active) </td>
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<td> Program Memory write byte enable (low active) </td>
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</tr>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
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<tr> <td colspan="4" align="center"> <b><i>Data Memory interface</i></b> </td></tr>
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<tr>
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<tr>
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<td> <a href="#5. Data Memory">dmem_addr</a> </td>
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<td> <a href="#5. Data Memory">dmem_addr</a> </td>
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| Line 136... |
Line 142... |
</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#5. Data Memory">dmem_wen</a> </td>
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<td> <a href="#5. Data Memory">dmem_wen</a> </td>
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<td> Output </td>
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<td> Output </td>
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<td> 2 </td>
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<td> 2 </td>
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<td> Data Memory write enable (low active) </td>
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<td> Data Memory write byte enable (low active) </td>
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</tr>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
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<tr> <td colspan="4" align="center"> <b><i>External Peripherals interface</i></b> </td></tr>
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<tr>
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<tr>
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<td> <a href="#6. Peripherals">per_addr</a> </td>
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<td> <a href="#6. Peripherals">per_addr</a> </td>
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<td> Output </td>
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<td> Output </td>
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<td> 8 </td>
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<td> 14 </td>
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<td> Peripheral address </td>
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<td> Peripheral address </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#6. Peripherals">per_din</a> </td>
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<td> <a href="#6. Peripherals">per_din</a> </td>
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<td> Output </td>
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<td> Output </td>
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| Line 165... |
Line 171... |
<td> Output </td>
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<td> Output </td>
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<td> 1 </td>
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<td> 1 </td>
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<td> Peripheral enable (high active) </td>
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<td> Peripheral enable (high active) </td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#6. Peripherals">per_wen</a> </td>
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<td> <a href="#6. Peripherals">per_we</a> </td>
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<td> Output </td>
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<td> Output </td>
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<td> 2 </td>
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<td> 2 </td>
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<td> Peripheral write enable (high active) </td>
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<td> Peripheral write byte enable (high active) </td>
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</tr>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
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<tr> <td colspan="4" align="center"> <b><i>Interrupts</i></b> </td></tr>
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<tr>
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<tr>
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<td> <a href="#7. Interrupts">irq</a> </td>
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<td> <a href="#7. Interrupts">irq</a> </td>
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| Line 193... |
Line 199... |
<td> Interrupt request accepted (one-hot signal) </td>
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<td> Interrupt request accepted (one-hot signal) </td>
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</tr>
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</tr>
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<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
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<tr> <td colspan="4" align="center"> <b><i>Serial Debug interface</i></b> </td></tr>
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<tr>
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<tr>
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<td> <a href="#8. Serial Debug Interface">dbg_en</a> </td>
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<td> Input </td>
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<td> 1 </td>
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<td> Debug interface enable (asynchronous) </td>
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</tr>
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<tr>
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<td> <a href="#8. Serial Debug Interface">dbg_freeze</a> </td>
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<td> <a href="#8. Serial Debug Interface">dbg_freeze</a> </td>
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<td> Output </td>
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<td> Output </td>
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<td> 1 </td>
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<td> 1 </td>
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<td> Freeze peripherals </td>
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<td> Freeze peripherals </td>
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</tr>
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</tr>
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| Line 208... |
Line 220... |
</tr>
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</tr>
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<tr>
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<tr>
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<td> <a href="#8. Serial Debug Interface">dbg_uart_rxd</a> </td>
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<td> <a href="#8. Serial Debug Interface">dbg_uart_rxd</a> </td>
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<td> Input </td>
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<td> Input </td>
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<td> 1 </td>
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<td> 1 </td>
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<td> Debug interface: UART RXD </td>
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<td> Debug interface: UART RXD (asynchronous) </td>
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</tr>
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</tr>
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</table>
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</table>
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<br />
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<br />
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<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
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<sup>1</sup>: This parameter is declared in the "openMSP430_defines.v" file and defines the RAM/ROM size.<br />
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<br />
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<br />
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Line 237... |
The different clocks in the design are managed by the Basic Clock Module:
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The different clocks in the design are managed by the Basic Clock Module:
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<br /><br />
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<br /><br />
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<img src="getimg.php?1246434498" width="75%" alt="Clock structure diagram" title="Clock structure diagram" />
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<img src="getimg.php?1246434498" width="75%" alt="Clock structure diagram" title="Clock structure diagram" />
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<br />
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<br />
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<ul>
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<ul>
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<li><b><font color="#0000b0">DCO_CLK</font></b>: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA might provide.<br />
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<li>
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<b><font color="#0000b0">CPU_EN</font></b>: this input port provide a hardware mean to stop or resume CPU execution. When unused, this port should be set to 1.
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<br /><br />
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</li>
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<li>
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<b><font color="#0000b0">DCO_CLK</font></b>: this input port is typically connected to a PLL, RC oscillator or any clock resource the target FPGA might provide.<br />
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From a synthesis tool perspective (ISE, Quartus, Libero, Design Compiler...), this the only port where a clock needs to be declared.
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From a synthesis tool perspective (ISE, Quartus, Libero, Design Compiler...), this the only port where a clock needs to be declared.
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<br /><br />
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<br /><br />
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</li>
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</li>
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<li>
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<li>
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<b><font color="#0000b0">LFXT_CLK</font></b>: if ACLK_EN or SMCLK_EN are going to be used in the project (for example through the Watchdog or TimerA peripherals), then this port needs to be connected to a clock running at least two time slower as DCO_CLK (typically 32kHz). It can be connected to 0 or 1 otherwise.
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<b><font color="#0000b0">LFXT_CLK</font></b>: if ACLK_EN or SMCLK_EN are going to be used in the project (for example through the Watchdog or TimerA peripherals), then this port needs to be connected to a clock running at least two time slower as DCO_CLK (typically 32kHz). It can be connected to 0 or 1 otherwise.
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| Line 258... |
Line 275... |
<ul>
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<ul>
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<li><b><font color="#0000b0">RESET_N</font></b>: this input port is typically connected to a board push button and is generally combined with the system power-on-reset.
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<li><b><font color="#0000b0">RESET_N</font></b>: this input port is typically connected to a board push button and is generally combined with the system power-on-reset.
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<br /><br />
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<br /><br />
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</li>
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</li>
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<li>
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<li>
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<b><font color="#00b000">PUC</font></b>: the Power-Up-Clear signal is asynchronously set with the reset pin (<i>RESET_N</i>), the watchdog reset or the serial debug interface reset. In order to get clean timings, it is synchronously cleared with MCLK's falling edge. As a general rule, this signal should be used as the reset of the <i>MCLK</i> clock domain.
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<b><font color="#00b000">PUC_RST</font></b>: the Power-Up-Clear signal is asynchronously set with the reset pin (<i>RESET_N</i>), the watchdog reset or the serial debug interface reset. In order to get clean timings, it is synchronously cleared with MCLK's falling edge. As a general rule, this signal should be used as the reset of the <i>MCLK</i> clock domain.
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<br /><br />
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<br /><br />
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</li>
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</li>
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</ul>
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</ul>
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The following waveform illustrates this:<br /><br />
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The following waveform illustrates this:<br /><br />
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<img src="getimg.php?1263320655" width="100%" alt="Waveforms: Resets - Jan 12. 2010" title="Waveforms: Resets - Jan 12. 2010" />
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<img src="getimg.php?1263320655" width="100%" alt="Waveforms: Resets - Jan 12. 2010" title="Waveforms: Resets - Jan 12. 2010" />
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| Line 350... |
Line 367... |
<ul>
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<ul>
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<li><b><font color="#00b000">PER_EN</font></b>: when this signal is active, read access are executed during the current <i>MCLK</i> cycle while write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is HIGH ACTIVE.
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<li><b><font color="#00b000">PER_EN</font></b>: when this signal is active, read access are executed during the current <i>MCLK</i> cycle while write access will be executed with the next <i>MCLK</i> rising edge. Note that this signal is HIGH ACTIVE.
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<br /><br />
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<br /><br />
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</li>
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</li>
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<li>
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<li>
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<b><font color="#00b000">PER_ADDR</font></b>: peripheral register address of the 16 bit word which is going to be accessed.<br />
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<b><font color="#00b000">PER_ADDR</font></b>: peripheral register address of the 16 bit word which is currently accessed. It is to be noted that a 14 bit address will always be provided from the openMSP430 to the peripheral in order to accommodate the biggest possible PER_SIZE Verilog configuration option (i.e. 32kB as opposed to 512B by default).<br />
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<b>Note:</b> in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@</i>
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<b>Note:</b> in order to calculate the core logical address from the peripheral register physical address, the formula goes as following: <i>LOGICAL@=2*PHYSICAL@</i>
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<br /><br />
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<br /><br />
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</li>
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</li>
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<li>
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<li>
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<b><font color="#0000b0">PER_DOUT</font></b>: the peripheral output word will be updated with every valid read/write access, it will be set to 0 otherwise.
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<b><font color="#0000b0">PER_DOUT</font></b>: the peripheral output word will be updated with every valid read/write access, it will be set to 0 otherwise.
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<br /><br />
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<br /><br />
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</li>
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</li>
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<li>
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<li>
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<b><font color="#00b000">PER_WE</font></b>: this signal selects which byte should be written during a valid access. PER_WEN[0] will activate a write on the lower byte, PER_WEN[1] a write on the upper byte. Note that these signals are HIGH ACTIVE.
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<b><font color="#00b000">PER_WE</font></b>: this signal selects which byte should be written during a valid access. PER_WE[0] will activate a write on the lower byte, PER_WE[1] a write on the upper byte. Note that these signals are HIGH ACTIVE.
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<br /><br />
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<br /><br />
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</li>
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</li>
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<li>
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<li>
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<b><font color="#00b000">PER_DIN</font></b>: the peripheral input word will be written with the valid write access according to the <i>PER_WEN</i> value.
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<b><font color="#00b000">PER_DIN</font></b>: the peripheral input word will be written with the valid write access according to the <i>PER_WEN</i> value.
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<br /><br />
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<br /><br />
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| Line 498... |
Line 515... |
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The serial debug interface module provides a two-wires communication bus for remote debugging and an additional freeze signal which might be useful for some peripherals.<br />
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The serial debug interface module provides a two-wires communication bus for remote debugging and an additional freeze signal which might be useful for some peripherals.<br />
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<br />
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<br />
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<ul>
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<ul>
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<li>
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<li>
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<b><font color="#0000b0">DBG_EN</font></b>: this signal allows the user to enable or disable the serial debug interface without interfering with the CPU execution. It is to be noted that when disabled (i.e. DBG_EN=0), the debug interface is held into reset.
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<br /><br />
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</li>
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<li>
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<b><font color="#00b000">DBG_FREEZE</font></b>: this signal will be set whenever the debug interface stops the CPU (and if the <i>FRZ_BRK_EN</i> field of the <a href="http://www.opencores.org/project,openmsp430,serial%20debug%20interface#2.2.2%20CPU_CTL">CPU_CTL</a> debug register is set). As its name implies, the purpose of <i>DBG_FREEZE</i> is to freeze a peripheral whenever the CPU is stopped by the software debugger.<br />
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<b><font color="#00b000">DBG_FREEZE</font></b>: this signal will be set whenever the debug interface stops the CPU (and if the <i>FRZ_BRK_EN</i> field of the <a href="http://www.opencores.org/project,openmsp430,serial%20debug%20interface#2.2.2%20CPU_CTL">CPU_CTL</a> debug register is set). As its name implies, the purpose of <i>DBG_FREEZE</i> is to freeze a peripheral whenever the CPU is stopped by the software debugger.<br />
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For example, it is used by the Watchdog timer in order to stop its free-running counter. This prevents the CPU from being reseted by the watchdog every times the user stops the CPU during a debugging session.
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For example, it is used by the Watchdog timer in order to stop its free-running counter. This prevents the CPU from being reseted by the watchdog every times the user stops the CPU during a debugging session.
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<br /><br />
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<br /><br />
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</li>
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</li>
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<li>
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<li>
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