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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
 
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd">
 
<html><head><title>openMSP430 Overview</title></head><body>
 
<html><head><title>openMSP430 Overview</title></head>
 
<br>
 
<body>
 
 
 
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  <tr>
 
 
 
    <td style="vertical-align: top;">
 
<h1>Introduction</h1>
 
<h1>Introduction</h1>
 
 
 
         The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is
 
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430 microcontroller family</a></b> and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.<br><br>
 
         compatible with Texas Instruments' <b><a href="http://www.ti.com/litv/pdf/slau049f">MSP430 microcontroller
 
The core comes with some peripherals (<b>16x16 Hardware Multiplier, </b>Watchdog, GPIO, TimerA, generic templates) and most notably with a two-wire <b>Serial Debug Interface</b> supporting the<b> <a href="http://sourceforge.net/apps/mediawiki/mspgcc/index.php?title=MSPGCC_Wiki" target="_blank">MSPGCC</a> GNU Debugger</b> (GDB) for in-system software debugging.
 
         family</a></b> and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.<br>
 
<br><br>
 
         <br>
 
 
 
         The core comes with some peripherals (<b>16x16 Hardware Multiplier, </b>Watchdog,
 
 
 
         GPIO, TimerA, generic templates) and most notably with a two-wire <b>Serial
 
 
 
         Debug Interface</b> supporting the<b> <a href="http://sourceforge.net/apps/mediawiki/mspgcc/index.php?title=MSPGCC_Wiki" target="_blank">MSPGCC</a> GNU Debugger</b> (GDB) for in-system
 
 
 
         software debugging. <br>
 
 
 
         <br>
 
While being fully FPGA friendly, this design is also particularly
 
While being fully FPGA friendly, this design is also particularly
 
suited for ASIC implementations (typically mixed signal ICs with strong area
 
         suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements).<br>
 
and low-power requirements).<br>
 
 
 
In a nutshell, the openMSP430 brings with it:<br>
 
In a nutshell, the openMSP430 brings with it:<br>
 
<ul>
 
<ul>
 
 
 
              <li>Low area (8k-Gates), without hidden extra infrastructure overhead (memory backbone, IRQ controller and watchdog timer are already included).</li>
 
  <li>Low area (8k-Gates), without hidden extra infrastructure
 
 
 
overhead (memory backbone, IRQ controller and watchdog timer are already
 
 
 
included).</li>
 
 
 
 
 
 
 
  <li>Excellent code density.</li>
 
  <li>Excellent code density.</li>
 
  <li>Good performances.</li>
 
  <li>Good performances.</li>
 
 
 
 
 
  <li>Build-in power and clock managment options.</li>
 
  <li>Build-in power and clock managment options.</li>
 
  <li>Multiple time <span style="font-weight: bold;">Silicon Proven</span>.<br>
 
              <li>Multiple time <span style="font-weight: bold;">Silicon Proven</span>.</li>
 
  </li>
 
 
 
</ul>
 
</ul>
 
 
 
    </td>
 
 
 
    <td style="vertical-align: top;">
 
 
 
         <table border="0" cellpadding="0" cellspacing="0">
 
 
 
         <tbody>
 
 
 
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         </tbody>
 
 
 
         </table>
 
 
 
    </td>
 
 
 
  </tr>
 
 
 
</tbody>
 
 
 
</table>
 
 
 
<br>
 
 
 
 
 
<h1>Download</h1>
 
<h1>Download</h1>
 
<h3>Design</h3>
 
<h3>Design</h3>
 
The complete tar archive of the project can be downloaded <a href="http://www.opencores.org/download,openmsp430">here</a> (OpenCores account required).<br>
 
The complete tar archive of the project can be downloaded <a href="http://www.opencores.org/download,openmsp430">here</a> (OpenCores account required).<br>
 
<br>
 
<br>
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      <li>Full instruction set support.</li>
 
      <li>Full instruction set support.</li>
 
      <li>Interrupts: IRQs (x14), NMI (x1).</li>
 
      <li>Interrupts: IRQs (x14), NMI (x1).</li>
 
      <li>Power saving modes.</li>
 
      <li>Power saving modes.</li>
 
      <li>Configurable memory size for both program and data.</li>
 
      <li>Configurable memory size for both program and data.</li>
 
      <li>Scalable peripheral address space.</li>
 
      <li>Scalable peripheral address space.</li>
 
      <li>Two-wire Serial Debug Interface (Nexus class 3, w/o trace) with GDB support.</li>
 
      <li>Two-wire Serial Debug Interface (Nexus class 3, w/o trace) with GDB support (I<sup>2</sup>C or UART based).</li>
 
      <li>FPGA friendly (option for single clock domain, no clock gate).</li>
 
      <li>FPGA friendly (option for single clock domain, no clock gate).</li>
 
      <li>ASIC friendly (options for full power &amp; clock management support).<br>
 
      <li>ASIC friendly (options for full power &amp; clock management support).<br>
 
      </li>
 
      </li>
 
 
 
 
 
      <li>Small size (Xilinx: 1650 LUTs / Altera: 1550 LEs / ASIC: 8k gates).</li>
 
      <li>Small size (Xilinx: 1650 LUTs / Altera: 1550 LEs / ASIC: 8k gates).</li>

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