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<h1>Introduction</h1>
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<h1>Introduction</h1>
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The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by an MSP430 toolchain in a cycle accurate way.
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The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by an MSP430 toolchain in a cycle accurate way.
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<br /><br />
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The core comes with some peripherals (GPIO, TimerA, generic templates) and a Serial Debug Interface for in-system software development.
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The core comes with some peripherals (16x16 Hardware Multiplier, GPIO, TimerA, generic templates) and a Serial Debug Interface for in-system software development.
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<h1>Download</h1>
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<h1>Download</h1>
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<h3>Design</h3>
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<h3>Design</h3>
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The complete tar archive of the project can be downloaded <a href="http://www.opencores.org/download,openmsp430">here</a> (OpenCores account required).<br />
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The complete tar archive of the project can be downloaded <a href="http://www.opencores.org/download,openmsp430">here</a> (OpenCores account required).<br />
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<li>IRQ and NMI support.</li>
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<li>IRQ and NMI support.</li>
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<li>Power saving modes functionality is supported.</li>
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<li>Power saving modes functionality is supported.</li>
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<li>Configurable memory size for both program and data.</li>
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<li>Configurable memory size for both program and data.</li>
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<li>Serial Debug Interface (Nexus class 3).</li>
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<li>Serial Debug Interface (Nexus class 3).</li>
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<li>FPGA friendly (single clock domain, no clock gate).</li>
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<li>FPGA friendly (single clock domain, no clock gate).</li>
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<li>Small size (uses ~43% of a XC3S200 Xilinx Spartan-3).</li>
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<li>Small size (Xilinx: 1650 LUTs / Altera: 1550 LEs / ASIC: 8k gates).</li>
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</ul>
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</ul>
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</li>
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</li>
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<br />
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<br />
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<li><b>Peripherals:</b>
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<li><b>Peripherals:</b>
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<ul>
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<ul>
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<li>16x16 Hardware Multiplier.</li>
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<li>Basic Clock Module.</li>
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<li>Basic Clock Module.</li>
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<li>Watchdog.</li>
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<li>Watchdog.</li>
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<li>Timer A.</li>
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<li>Timer A.</li>
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<li>GPIO (port 1 to 6).</li>
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<li>GPIO (port 1 to 6).</li>
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<li>Templates for 8 and 16 bit peripherals (under BSD license).</li>
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</ul>
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</ul>
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</li>
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</li>
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</ul>
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</ul>
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<h2>Limitations</h2>
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<h2>Limitations</h2>
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<ul>
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<ul>
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