| Line 90... |
Line 90... |
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
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<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
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</tr>
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</tr>
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<tr align="center">
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<tr align="center">
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<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_LO</a></font></td>
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<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_LO</a></font></td>
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<td><font size="-1">0x00</font></td>
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<td><font size="-1">0x00</font></td>
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<td colspan="16"><font size="-5">DMEM_AWIDTH</font></td>
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<td colspan="7"><font size="-5">PER_SPACE</font></td>
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<td colspan="5"><font size="-5">USER_VERSION</font></td>
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<td colspan="1"><font size="-5">ASIC</font></td>
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<td colspan="3"><font size="-5">CPU_VERSION</font></td>
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</tr>
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</tr>
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<tr align="center">
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<tr align="center">
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<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_HI</a></font></td>
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<td><font size="-1"><a href="#2.2.1 CPU_ID">CPU_ID_HI</a></font></td>
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<td><font size="-1">0x01</font></td>
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<td><font size="-1">0x01</font></td>
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<td colspan="16"><font size="-5">PMEM_AWIDTH</font></td>
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<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
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<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
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<td colspan="1"><font size="-5">MPY</font></td>
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</tr>
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</tr>
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<tr align="center">
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<tr align="center">
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<td><font size="-1"><a href="#2.2.2 CPU_CTL">CPU_CTL</a></font></td>
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<td><font size="-1"><a href="#2.2.2 CPU_CTL">CPU_CTL</a></font></td>
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<td><font size="-1">0x02</font></td>
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<td><font size="-1">0x02</font></td>
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<td colspan="9"><font size="-5">Reserved</font></td>
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<td colspan="9"><font size="-5">Reserved</font></td>
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| Line 295... |
Line 300... |
<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
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<td><font size="-1"> 1</font></td><td><font size="-1"> 0</font></td>
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</tr>
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</tr>
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<tr align="center">
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<tr align="center">
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<td><font size="-1">CPU_ID_LO</font></td>
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<td><font size="-1">CPU_ID_LO</font></td>
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<td><font size="-1">0x00</font></td>
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<td><font size="-1">0x00</font></td>
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<td colspan="16"><font size="-5">DMEM_AWIDTH</font></td>
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<td colspan="7"><font size="-5">PER_SPACE</font></td>
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<td colspan="5"><font size="-5">USER_VERSION</font></td>
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<td colspan="1"><font size="-5">ASIC</font></td>
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<td colspan="3"><font size="-5">CPU_VERSION</font></td>
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</tr>
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</tr>
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<tr align="center">
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<tr align="center">
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<td><font size="-1">CPU_ID_HI</font></td>
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<td><font size="-1">CPU_ID_HI</font></td>
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<td><font size="-1">0x01</font></td>
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<td><font size="-1">0x01</font></td>
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<td colspan="16"><font size="-5">PMEM_AWIDTH</font></td>
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<td colspan="6"><font size="-5">PMEM_SIZE</font></td>
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<td colspan="9"><font size="-5">DMEM_SIZE</font></td>
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<td colspan="1"><font size="-5">MPY</font></td>
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</tr>
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</tr>
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</table>
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</table>
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<br />
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<br />
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<table border="0">
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<table border="0">
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<tr>
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<tr>
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<td> </td><td valign="top"><li><b>PMEM_AWIDTH</b></li></td>
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<td> </td><td valign="top"><li><b>CPU_VERSION</b></li></td>
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<td>: Program memory size in byte for the current implementation</td>
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<td>: Current CPU version (currently 1)</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td valign="top"><li><b>DMEM_AWIDTH</b></li></td>
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<td> </td><td valign="top"><li><b>ASIC</b></li></td>
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<td>: Data memory size in byte for the current implementation.</td>
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<td>: Defines if the ASIC specific features are enabled in the current openMSP430 implementation.</td>
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</tr>
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<tr>
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<td> </td><td valign="top"><li><b>USER_VERSION</b></li></td>
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<td>: Reflects the value defined in the <b>openMSP430_defines.v</b> file.</td>
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</tr>
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<tr>
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<td> </td><td valign="top"><li><b>PER_SPACE</b></li></td>
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<td>: Peripheral address space for the current implementation (byte size = PER_SPACE*512)</td>
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</tr>
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<tr>
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<td> </td><td valign="top"><li><b>MPY</b></li></td>
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<td>: This bit is set if the hardware multiplier is included in the current implementation</td>
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</tr>
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<tr>
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<td> </td><td valign="top"><li><b>DMEM_SIZE</b></li></td>
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<td>: Data memory size for the current implementation (byte size = DMEM_SIZE*128)</td>
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</tr>
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<tr>
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<td> </td><td valign="top"><li><b>PMEM_SIZE</b></li></td>
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<td>: Progam memory size for the current implementation (byte size = PMEM_SIZE*1024)</td>
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</tr>
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</tr>
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</table>
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</table>
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|
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<a name="2.2.2 CPU_CTL"></a>
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<a name="2.2.2 CPU_CTL"></a>
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<h3>2.2.2 CPU_CTL</h3>
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<h3>2.2.2 CPU_CTL</h3>
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| Line 690... |
Line 720... |
<td>: 0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)</td>
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<td>: 0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td> </td>
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<td> </td><td> </td>
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<td> 1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode)
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<td> 1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode)
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<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
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<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
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</td>
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</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td valign="top"><li><b>INST_EN</b></li></td>
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<td> </td><td valign="top"><li><b>INST_EN</b></li></td>
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<td>: 0 - Checks are done on the execution unit (data flow).</td>
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<td>: 0 - Checks are done on the execution unit (data flow).</td>
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| Line 762... |
Line 792... |
<td>: This bit is set whenever the CPU performs a write access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[1]=1).</td>
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<td>: This bit is set whenever the CPU performs a write access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[1]=1).</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td valign="top"><li><b>RANGE_RD</b></li></td>
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<td> </td><td valign="top"><li><b>RANGE_RD</b></li></td>
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<td>: This bit is set whenever the CPU performs a read access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[0]=1).
|
<td>: This bit is set whenever the CPU performs a read access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[0]=1).
|
<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
|
<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `DBG_HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
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</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td> </td><td valign="top"><li><b>ADDR1_WR</b></li></td>
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<td> </td><td valign="top"><li><b>ADDR1_WR</b></li></td>
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<td>: This bit is set whenever the CPU performs a write access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
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<td>: This bit is set whenever the CPU performs a write access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
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</tr>
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</tr>
|
