| Line 1078... |
Line 1078... |
<h2>3.1 Serial communication protocol: 8N1</h2>
|
<h2>3.1 Serial communication protocol: 8N1</h2>
|
There are plenty tutorials on Internet regarding RS232 based protocols.
|
There are plenty tutorials on Internet regarding RS232 based protocols.
|
However, here is quick recap about 8N1 (1 Start bit, 8 Data bits, No
|
However, here is quick recap about 8N1 (1 Start bit, 8 Data bits, No
|
Parity, 1 Stop bit):<br>
|
Parity, 1 Stop bit):<br>
|
<br>
|
<br>
|
<img src="usercontent,img,1247419201" alt="8N1 Serial Protocol" title="8N1 Serial Protocol">
|
<img src="http://opencores.org/usercontent,img,1247419201" alt="8N1 Serial Protocol" title="8N1 Serial Protocol">
|
<br>
|
<br>
|
As you can see in the above diagram, data transmission starts with a
|
As you can see in the above diagram, data transmission starts with a
|
Start bit, followed by the data bits (LSB sent first and MSB sent
|
Start bit, followed by the data bits (LSB sent first and MSB sent
|
last), and ends with a "Stop" bit.
|
last), and ends with a "Stop" bit.
|
<a name="3.2 Synchronization frame"></a>
|
<a name="3.2 Synchronization frame"></a>
|
<h2>3.2 Synchronization frame</h2>After a POR, the Serial Debug
|
<h2>3.2 Synchronization frame</h2>After a POR, the Serial Debug
|
Interface expects a synchronization frame from the host computer in
|
Interface expects a synchronization frame from the host computer in
|
order to determine the communication speed (i.e. the baud rate).<br>
|
order to determine the communication speed (i.e. the baud rate).<br>
|
The synchronization frame looks as following:
|
The synchronization frame looks as following:
|
<br>
|
<br>
|
<img src="usercontent,img,1247420610" alt="Debug Synchronization Frame" title="Debug Synchronization Frame">
|
<img src="http://opencores.org/usercontent,img,1247420610" alt="Debug Synchronization Frame" title="Debug Synchronization Frame">
|
<br>
|
<br>
|
As you can see, the host simply sends the 0x80 value. The openMSP430
|
As you can see, the host simply sends the 0x80 value. The openMSP430
|
will then measure the time between the falling and rising edge, divide
|
will then measure the time between the falling and rising edge, divide
|
it by 8 and automatically deduce the baud rate it should use to
|
it by 8 and automatically deduce the baud rate it should use to
|
properly communicate with the host.
|
properly communicate with the host.
|
| Line 1109... |
Line 1109... |
data frames after receiving the command.
|
data frames after receiving the command.
|
<a name="3.3.1 Command Frame"></a>
|
<a name="3.3.1 Command Frame"></a>
|
<h3>3.3.1 Command Frame</h3>
|
<h3>3.3.1 Command Frame</h3>
|
The command frame looks as following:
|
The command frame looks as following:
|
<br>
|
<br>
|
<img src="usercontent,img,1247427400" alt="Debug Command Frame" title="Debug Command Frame">
|
<img src="http://opencores.org/usercontent,img,1247427400" alt="Debug Command Frame" title="Debug Command Frame">
|
<br>
|
<br>
|
<table border="0">
|
<table border="0">
|
<tbody><tr>
|
<tbody><tr>
|
<td> </td><td valign="top"><li><b>WR</b></li></td>
|
<td> </td><td valign="top"><li><b>WR</b></li></td>
|
<td>: Perform a Write access when set. Read otherwise.</td>
|
<td>: Perform a Write access when set. Read otherwise.</td>
|
| Line 1130... |
Line 1130... |
|
|
<a name="3.3.2 Write access"></a>
|
<a name="3.3.2 Write access"></a>
|
<h3>3.3.2 Write access</h3>
|
<h3>3.3.2 Write access</h3>
|
A write access transaction looks like this:
|
A write access transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1247428987" alt="Debug Write Transaction" title="Debug Write Transaction">
|
<img src="http://opencores.org/usercontent,img,1247428987" alt="Debug Write Transaction" title="Debug Write Transaction">
|
|
|
<a name="3.3.3 Read access"></a>
|
<a name="3.3.3 Read access"></a>
|
<h3>3.3.3 Read access</h3>
|
<h3>3.3.3 Read access</h3>
|
A read access transaction looks like this:
|
A read access transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1247429086" alt="Debug Read Transaction" title="Debug Read Transaction">
|
<img src="http://opencores.org/usercontent,img,1247429086" alt="Debug Read Transaction" title="Debug Read Transaction">
|
|
|
<a name="3.4 Read/Write burst implementation for the CPU Memory access"></a>
|
<a name="3.4 Read/Write burst implementation for the CPU Memory access"></a>
|
<h2>3.4 Read/Write burst implementation for the CPU Memory access</h2>In
|
<h2>3.4 Read/Write burst implementation for the CPU Memory access</h2>In
|
order to optimize the data burst transactions for the UART, read/write
|
order to optimize the data burst transactions for the UART, read/write
|
access are not done by reading or writing the MEM_DATA register.<br>
|
access are not done by reading or writing the MEM_DATA register.<br>
|
| Line 1148... |
Line 1148... |
|
|
<a name="3.4.1 Write Burst access"></a>
|
<a name="3.4.1 Write Burst access"></a>
|
<h3>3.4.1 Write Burst access</h3>
|
<h3>3.4.1 Write Burst access</h3>
|
A write burst transaction looks like this:
|
A write burst transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1247430408" alt="Debug Write Burst Transaction" title="Debug Write Burst Transaction">
|
<img src="http://opencores.org/usercontent,img,1247430408" alt="Debug Write Burst Transaction" title="Debug Write Burst Transaction">
|
|
|
<a name="3.4.2 Read Burst access"></a>
|
<a name="3.4.2 Read Burst access"></a>
|
<h3>3.4.2 Read Burst access</h3>
|
<h3>3.4.2 Read Burst access</h3>
|
A read burst transaction looks like this:
|
A read burst transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1247430449" alt="Debug Read Burst Transaction" title="Debug Read Burst Transaction">
|
<img src="http://opencores.org/usercontent,img,1247430449" alt="Debug Read Burst Transaction" title="Debug Read Burst Transaction">
|
|
|
<a name="4. Debug Communication Interface: I2C"></a>
|
<a name="4. Debug Communication Interface: I2C"></a>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<h1>4. Debug Communication Interface: I2C</h1>
|
<h1>4. Debug Communication Interface: I2C</h1>
|
With its I2C interface, the openMSP430 debug unit can communicate with the host computer using
|
With its I2C interface, the openMSP430 debug unit can communicate with the host computer using
|
| Line 1170... |
Line 1170... |
<a name="4.1 I2C communication protocol"></a>
|
<a name="4.1 I2C communication protocol"></a>
|
<h2>4.1 I2C communication protocol</h2>
|
<h2>4.1 I2C communication protocol</h2>
|
There are plenty tutorials on Internet regarding the I2C protocol (see the official <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I2C specification</a> for more info).<br>
|
There are plenty tutorials on Internet regarding the I2C protocol (see the official <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I2C specification</a> for more info).<br>
|
A simple byte read or write frame looks as following:<br>
|
A simple byte read or write frame looks as following:<br>
|
<br>
|
<br>
|
<img src="usercontent,img,1352582784" alt="I2C Protocol" title="I2C Protocol" width="80%">
|
<img src="http://opencores.org/usercontent,img,1352582784" alt="I2C Protocol" title="I2C Protocol" width="80%">
|
<br><a name="4.2 Synchronization frame"></a>
|
<br><a name="4.2 Synchronization frame"></a>
|
<h2>4.2 Synchronization frame</h2>
|
<h2>4.2 Synchronization frame</h2>
|
Unlike the UART interface, the I2C is a synchronous communication protocol.<br>
|
Unlike the UART interface, the I2C is a synchronous communication protocol.<br>
|
A synchronization frame is therefore not required.<br><br>
|
A synchronization frame is therefore not required.<br><br>
|
|
|
| Line 1186... |
Line 1186... |
data frames after receiving the command.
|
data frames after receiving the command.
|
<a name="4.3.1 Command Frame"></a>
|
<a name="4.3.1 Command Frame"></a>
|
<h3>4.3.1 Command Frame</h3>
|
<h3>4.3.1 Command Frame</h3>
|
The command frame looks as following:
|
The command frame looks as following:
|
<br>
|
<br>
|
<img src="usercontent,img,1352584261" alt="Debug command frame" title="Debug command frame" width="100%">
|
<img src="http://opencores.org/usercontent,img,1352584261" alt="Debug command frame" title="Debug command frame" width="100%">
|
<br>
|
<br>
|
<table border="0">
|
<table border="0">
|
<tbody><tr>
|
<tbody><tr>
|
<td> </td><td valign="top"><li><b>WR</b></li></td>
|
<td> </td><td valign="top"><li><b>WR</b></li></td>
|
<td>: Perform a Write access when set. Read otherwise.</td>
|
<td>: Perform a Write access when set. Read otherwise.</td>
|
| Line 1207... |
Line 1207... |
|
|
<a name="4.3.2 Write access"></a>
|
<a name="4.3.2 Write access"></a>
|
<h3>4.3.2 Write access</h3>
|
<h3>4.3.2 Write access</h3>
|
A write access transaction looks like this:
|
A write access transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1352586896" alt="I2C Debug Write Transaction" title="I2C Debug Write Transaction" width="100%">
|
<img src="http://opencores.org/usercontent,img,1352586896" alt="I2C Debug Write Transaction" title="I2C Debug Write Transaction" width="100%">
|
|
|
<a name="4.3.3 Read access"></a>
|
<a name="4.3.3 Read access"></a>
|
<h3>4.3.3 Read access</h3>
|
<h3>4.3.3 Read access</h3>
|
A read access transaction looks like this:
|
A read access transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1352586064" alt="I2C Debug Read Transaction" title="I2C Debug Read Transaction" width="100%">
|
<img src="http://opencores.org/usercontent,img,1352586064" alt="I2C Debug Read Transaction" title="I2C Debug Read Transaction" width="100%">
|
|
|
<a name="4.4 Read/Write burst implementation for the CPU Memory access"></a>
|
<a name="4.4 Read/Write burst implementation for the CPU Memory access"></a>
|
<h2>4.4 Read/Write burst implementation for the CPU Memory access</h2>In
|
<h2>4.4 Read/Write burst implementation for the CPU Memory access</h2>In
|
order to optimize the data burst transactions for the I2C, read/write
|
order to optimize the data burst transactions for the I2C, read/write
|
access are not done by reading or writing the MEM_DATA register.<br>
|
access are not done by reading or writing the MEM_DATA register.<br>
|
| Line 1225... |
Line 1225... |
|
|
<a name="4.4.1 Write Burst access"></a>
|
<a name="4.4.1 Write Burst access"></a>
|
<h3>4.4.1 Write Burst access</h3>
|
<h3>4.4.1 Write Burst access</h3>
|
A write burst transaction looks like this:
|
A write burst transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1352673100" alt="I2C Debug Write Burst Transaction" title="I2C Debug Write Burst Transaction" width="100%">
|
<img src="http://opencores.org/usercontent,img,1352673100" alt="I2C Debug Write Burst Transaction" title="I2C Debug Write Burst Transaction" width="100%">
|
|
|
<a name="4.4.2 Read Burst access"></a>
|
<a name="4.4.2 Read Burst access"></a>
|
<h3>4.4.2 Read Burst access</h3>
|
<h3>4.4.2 Read Burst access</h3>
|
A read burst transaction looks like this:
|
A read burst transaction looks like this:
|
<br>
|
<br>
|
<img src="usercontent,img,1352672466" alt="I2C Debug Read Burst Transaction" title="I2C Debug Read Burst Transaction" width="100%">
|
<img src="http://opencores.org/usercontent,img,1352672466" alt="I2C Debug Read Burst Transaction" title="I2C Debug Read Burst Transaction" width="100%">
|
|
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
<div style="text-align: right;"><a href="#TOC">Top</a></div>
|
|
|
</body></html>
|
</body></html>
|
No newline at end of file
|
No newline at end of file
|
