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Line 697... |
<td> </td><td valign="top"><li><b>RANGE_MODE</b></li></td>
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<td> </td><td valign="top"><li><b>RANGE_MODE</b></li></td>
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<td>: 0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)</td>
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<td>: 0 - Address match on BRK_ADDR0 or BRK_ADDR1 (normal mode)</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td> </td>
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<td> </td><td> </td>
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<td> 1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode)</td>
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<td> 1 - Address match on BRK_ADDR0→BRK_ADDR1 range (range mode)
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<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
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</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td valign="top"><li><b>INST_EN</b></li></td>
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<td> </td><td valign="top"><li><b>INST_EN</b></li></td>
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<td>: 0 - Checks are done on the execution unit (data flow).</td>
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<td>: 0 - Checks are done on the execution unit (data flow).</td>
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</tr>
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</tr>
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| Line 767... |
Line 769... |
<td> </td><td valign="top"><li><b>RANGE_WR</b></li></td>
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<td> </td><td valign="top"><li><b>RANGE_WR</b></li></td>
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<td>: This bit is set whenever the CPU performs a write access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[1]=1).</td>
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<td>: This bit is set whenever the CPU performs a write access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[1]=1).</td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td valign="top"><li><b>RANGE_RD</b></li></td>
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<td> </td><td valign="top"><li><b>RANGE_RD</b></li></td>
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<td>: This bit is set whenever the CPU performs a read access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[0]=1).</td>
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<td>: This bit is set whenever the CPU performs a read access within the BRKx_ADDR0→BRKx_ADDR1 range (valid if RANGE_MODE=1 and ACCESS_MODE[0]=1).
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<br /><font color="red"><b>Note</b>: range mode is not supported by the core unless the `HWBRK_RANGE define is set to 1'b1 in the <i>openMSP430_define.v</i> file.</font></td>
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</tr>
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</tr>
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<tr>
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<tr>
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<td> </td><td valign="top"><li><b>ADDR1_WR</b></li></td>
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<td> </td><td valign="top"><li><b>ADDR1_WR</b></li></td>
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<td>: This bit is set whenever the CPU performs a write access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
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<td>: This bit is set whenever the CPU performs a write access at the BRKx_ADDR1 address (valid if RANGE_MODE=0 and ACCESS_MODE[1]=1).</td>
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</tr>
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</tr>
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