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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] [README] - Diff between revs 29 and 221

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This is OpenMSP430 core+peripherals implementation adapted for Altera DE1 board.
 
 
 
It is based on original Olivier's adaptation for Diligent S3 board, but has following distinctions:
 
 
 
1. Fixed 7segment core, since DE1 has non-muxed digits.
 
2. It is adapted for MegaWizard-generated 16-bit wide on-chip ROMs and RAMs.
 
3. Debug ROM write is removed (although it shouldn't be a problem to return it back).
 
   Anyway I haven't used any debug features.
 
4. As an alternative to the embedded synchronous RAM, there is ext_de1_sram module that
 
   allows core to access external on-board static RAM.
 
5. Core is configured to have non-standard ROM and RAM sizes (4kB and 1kB), so make
 
   sure the OpenMSP430_defines.v file is properly updated
 
6. There is new software project that uses custom linker script to compile for non-standard
 
   ROM and RAM sizes.
 
 
 
Any questions? lvd.mhm@gmail.com
 
 

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