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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [dbg_uart_tasks.v] - Diff between revs 108 and 136

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Rev 108 Rev 136
Line 76... Line 76...
// If the auto synchronization mode is set, then the communication speed
// If the auto synchronization mode is set, then the communication speed
// is configured by the testbench.
// is configured by the testbench.
// If not, the values from the openMSP430.inc file are taken over.
// If not, the values from the openMSP430.inc file are taken over.
`ifdef DBG_UART_AUTO_SYNC
`ifdef DBG_UART_AUTO_SYNC
parameter UART_BAUD = 4000000;
parameter UART_BAUD = 4000000;
parameter UART_CNT  = ((20000000/UART_BAUD)-1);
integer   UART_PERIOD = 1000000000/UART_BAUD;
`else
`else
parameter UART_CNT  = `DBG_UART_CNT;
integer   UART_PERIOD = `DBG_UART_CNT;
`endif
`endif
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Receive UART frame from CPU Debug interface (8N1)
// Receive UART frame from CPU Debug interface (8N1)
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
task dbg_uart_rx;
task dbg_uart_rx;
      output [7:0] dbg_rxbuf;
      output [7:0] dbg_rxbuf;
 
 
      reg [7:0] dbg_rxbuf;
      reg [7:0] dbg_rxbuf;
      reg [7:0] rxbuf;
      reg [7:0] rxbuf;
      integer   rxcnt;
      integer   rxcnt;
      begin
      begin
 
      #(1);
 
      dbg_uart_rx_busy = 1'b1;
         @(negedge dbg_uart_txd);
         @(negedge dbg_uart_txd);
         dbg_rxbuf = 0;
         dbg_rxbuf = 0;
         rxbuf = 0;
         rxbuf = 0;
         repeat((UART_CNT+1)/2) @(posedge mclk);
      #(3*UART_PERIOD/2);
         for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
         for (rxcnt = 0; rxcnt < 8; rxcnt = rxcnt + 1)
           begin
           begin
              repeat(UART_CNT+1) @(posedge mclk);
 
              rxbuf = {dbg_uart_txd, rxbuf[7:1]};
              rxbuf = {dbg_uart_txd, rxbuf[7:1]};
 
           #(UART_PERIOD);
           end
           end
         dbg_rxbuf = rxbuf;
         dbg_rxbuf = rxbuf;
 
      dbg_uart_rx_busy = 1'b0;
      end
      end
endtask
endtask
 
 
task dbg_uart_rx16;
task dbg_uart_rx16;
 
 
Line 136... Line 140...
      input  [7:0] txbuf;
      input  [7:0] txbuf;
 
 
      reg [9:0] txbuf_full;
      reg [9:0] txbuf_full;
      integer   txcnt;
      integer   txcnt;
      begin
      begin
         dbg_uart_rxd = 1'b1;
      #(1);
 
      dbg_uart_tx_busy = 1'b1;
 
      dbg_uart_rxd_pre = 1'b1;
         txbuf_full   = {1'b1, txbuf, 1'b0};
         txbuf_full   = {1'b1, txbuf, 1'b0};
         for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
         for (txcnt = 0; txcnt < 10; txcnt = txcnt + 1)
           begin
           begin
              repeat(UART_CNT+1) @(posedge mclk);
           #(UART_PERIOD);
              dbg_uart_rxd =  txbuf_full[txcnt];
           dbg_uart_rxd_pre =  txbuf_full[txcnt];
           end
           end
 
      dbg_uart_tx_busy = 1'b0;
      end
      end
endtask
endtask
 
 
task dbg_uart_tx16;
task dbg_uart_tx16;
      input  [15:0] txbuf;
      input  [15:0] txbuf;
Line 155... Line 162...
         dbg_uart_tx(txbuf[7:0]);
         dbg_uart_tx(txbuf[7:0]);
         dbg_uart_tx(txbuf[15:8]);
         dbg_uart_tx(txbuf[15:8]);
      end
      end
endtask
endtask
 
 
 
always @(posedge mclk or posedge dbg_rst)
 
  if (dbg_rst)
 
    begin
 
       dbg_uart_rxd_sel <= 1'b0;
 
       dbg_uart_rxd_dly <= 1'b1;
 
    end
 
  else if (dbg_en)
 
    begin
 
       dbg_uart_rxd_sel <= dbg_uart_rxd_meta ? $random : 1'b0;
 
       dbg_uart_rxd_dly <= dbg_uart_rxd_pre;
 
    end
 
 
 
assign dbg_uart_rxd = dbg_uart_rxd_sel ? dbg_uart_rxd_dly : dbg_uart_rxd_pre;
 
 
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Write to Debug register
// Write to Debug register
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
task dbg_uart_wr;
task dbg_uart_wr;
Line 192... Line 213...
 
 
         dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
         dbg_uart_buf = {rxbuf_hi, rxbuf_lo};
      end
      end
endtask
endtask
 
 
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//----------------------------------------------------------------------------
 
// Send synchronization frame
 
//----------------------------------------------------------------------------
 
task dbg_uart_sync;
 
   begin
 
      dbg_uart_tx(DBG_SYNC);
 
      repeat(10) @(posedge mclk);
 
   end
 
endtask
 
 
 
 
 
 
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