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Line 51... |
inst_pc, // Instruction Program counter
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inst_pc, // Instruction Program counter
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inst_short, // Currently executed instruction (short version)
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inst_short, // Currently executed instruction (short version)
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// INPUTs
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// INPUTs
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mclk, // Main system clock
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mclk, // Main system clock
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puc // Main system reset
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puc_rst // Main system reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//============
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//============
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output [8*32-1:0] e_state; // Execution state
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output [8*32-1:0] e_state; // Execution state
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output [8*32-1:0] inst_short; // Currently executed instruction (short version)
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output [8*32-1:0] inst_short; // Currently executed instruction (short version)
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// INPUTs
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// INPUTs
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//============
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//============
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input mclk; // Main system clock
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input mclk; // Main system clock
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input puc; // Main system reset
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input puc_rst; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) ASCII FORMATING FUNCTIONS
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// 1) ASCII FORMATING FUNCTIONS
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//=============================================================================
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//=============================================================================
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Line 169... |
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// Count instruction number & cycles
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// Count instruction number & cycles
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//====================================
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//====================================
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reg [31:0] inst_number;
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reg [31:0] inst_number;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) inst_number <= 0;
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if (puc_rst) inst_number <= 0;
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else if (decode) inst_number <= inst_number+1;
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else if (decode) inst_number <= inst_number+1;
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reg [31:0] inst_cycle;
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reg [31:0] inst_cycle;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) inst_cycle <= 0;
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if (puc_rst) inst_cycle <= 0;
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else if (decode) inst_cycle <= 0;
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else if (decode) inst_cycle <= 0;
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else inst_cycle <= inst_cycle+1;
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else inst_cycle <= inst_cycle+1;
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// Decode instruction
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// Decode instruction
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//====================================
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//====================================
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// Buffer opcode
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// Buffer opcode
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reg [15:0] opcode;
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reg [15:0] opcode;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) opcode <= 0;
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if (puc_rst) opcode <= 0;
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else if (decode) opcode <= ir;
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else if (decode) opcode <= ir;
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// Interrupts
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// Interrupts
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reg irq;
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reg irq;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) irq <= 1'b1;
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if (puc_rst) irq <= 1'b1;
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else if (decode) irq <= irq_detect;
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else if (decode) irq <= irq_detect;
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// Instruction type
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// Instruction type
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reg [8*32-1:0] inst_type;
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reg [8*32-1:0] inst_type;
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always @(opcode or irq)
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always @(opcode or irq)
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Line 436... |
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// Instruction program counter
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// Instruction program counter
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//================================
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//================================
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reg [15:0] inst_pc;
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reg [15:0] inst_pc;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) inst_pc <= 16'h0000;
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if (puc_rst) inst_pc <= 16'h0000;
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else if (decode) inst_pc <= pc;
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else if (decode) inst_pc <= pc;
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endmodule // msp_debug
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endmodule // msp_debug
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