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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [msp_debug.v] - Diff between revs 111 and 136

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Rev 111	Rev 136
Line 147...	Line 147...

`reg [8*32-1:0] e_state;`	`reg [8*32-1:0] e_state;`

`always @(e_state_bin)`	`always @(e_state_bin)`
`case(e_state_bin)`	`case(e_state_bin)`
`4'h0 : e_state = "IRQ_0";`	`4'h2 : e_state = "IRQ_0";`
`4'h1 : e_state = "IRQ_1";`	`4'h1 : e_state = "IRQ_1";`
`4'h2 : e_state = "IRQ_2";`	`4'h0 : e_state = "IRQ_2";`
`4'h3 : e_state = "IRQ_3";`	`4'h3 : e_state = "IRQ_3";`
`4'h4 : e_state = "IRQ_4";`	`4'h4 : e_state = "IRQ_4";`
`4'h5 : e_state = "SRC_AD";`	`4'h5 : e_state = "SRC_AD";`
`4'h6 : e_state = "SRC_RD";`	`4'h6 : e_state = "SRC_RD";`
`4'h7 : e_state = "SRC_WR";`	`4'h7 : e_state = "SRC_WR";`

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