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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [registers.v] - Diff between revs 111 and 136

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Rev 111 Rev 136
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//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// 
// 
// *File Name: registers.v
// *File Name: registers.v
// 
// 
// *Module Description:
// *Module Description:
//                      openMSP430 testbench
//                      Direct connections to internal registers & memory.
 
//
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
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wire  [15:0] irq_vect_02 = pmem[(1<<(`PMEM_MSB+1))-14]; // IRQ  2
wire  [15:0] irq_vect_02 = pmem[(1<<(`PMEM_MSB+1))-14]; // IRQ  2
wire  [15:0] irq_vect_01 = pmem[(1<<(`PMEM_MSB+1))-15]; // IRQ  1
wire  [15:0] irq_vect_01 = pmem[(1<<(`PMEM_MSB+1))-15]; // IRQ  1
wire  [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ  0
wire  [15:0] irq_vect_00 = pmem[(1<<(`PMEM_MSB+1))-16]; // IRQ  0
 
 
 
 
 
// Interrupt detection
 
wire              nmi_detect  = dut.openMSP430_0.frontend_0.nmi_pnd;
 
wire              irq_detect  = dut.openMSP430_0.frontend_0.irq_detect;
 
 
 
// Debug interface
 
wire              dbg_en      = dut.openMSP430_0.dbg_en;
 
wire              dbg_clk     = dut.openMSP430_0.clock_module_0.dbg_clk;
 
wire              dbg_rst     = dut.openMSP430_0.clock_module_0.dbg_rst;
 
 
 
 
// CPU internals
// CPU internals
//======================
//======================
 
 
wire mclk     = dut.openMSP430_0.mclk;
wire mclk     = dut.openMSP430_0.mclk;
wire puc_rst  = dut.openMSP430_0.puc_rst;
wire puc_rst  = dut.openMSP430_0.puc_rst;

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