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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 98 and 104

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Rev 98 Rev 104
Line 34... Line 34...
// $Rev: 37 $
// $Rev: 37 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
 
`ifdef OMSP_NO_INCLUDE
 
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
`endif
 
 
module  tb_openMSP430_fpga;
module  tb_openMSP430_fpga;
 
 
//
//
// Wire & Register definition
// Wire & Register definition

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