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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 104 and 107

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Rev 104 Rev 107
Line 57... Line 57...
 
 
// LEDs
// LEDs
wire        [9:0] led;
wire        [9:0] led;
 
 
// UART
// UART
reg               uart_rx;
reg               dbg_uart_rxd;
wire              uart_tx;
wire              dbg_uart_txd;
 
reg        [15:0] dbg_uart_buf;
 
 
// Core debug signals
// Core debug signals
wire   [8*32-1:0] i_state;
wire   [8*32-1:0] i_state;
wire   [8*32-1:0] e_state;
wire   [8*32-1:0] e_state;
wire       [31:0] inst_cycle;
wire       [31:0] inst_cycle;
Line 83... Line 84...
//------------------------------
//------------------------------
 
 
// CPU & Memory registers
// CPU & Memory registers
`include "registers.v"
`include "registers.v"
 
 
 
// Debug interface tasks
 
`include "dbg_uart_tasks.v"
 
 
// Verilog stimulus
// Verilog stimulus
`include "stimulus.v"
`include "stimulus.v"
 
 
//
//
// Initialize Program Memory
// Initialize Program Memory
Line 142... Line 146...
initial
initial
  begin
  begin
     error         = 0;
     error         = 0;
     stimulus_done = 1;
     stimulus_done = 1;
     switch        = 10'h000;
     switch        = 10'h000;
     uart_rx       = 1'b0;
     dbg_uart_rxd  = 1'b1;
  end
  end
 
 
//
//
// openMSP430 FPGA Instance
// openMSP430 FPGA Instance
//----------------------------------
//----------------------------------
Line 159... Line 163...
    .led          (led),            // Board LEDs
    .led          (led),            // Board LEDs
    .sclk_x       (sclk_x),         // SPI Serial Clock
    .sclk_x       (sclk_x),         // SPI Serial Clock
    .sclk_y       (sclk_y),         // SPI Serial Clock
    .sclk_y       (sclk_y),         // SPI Serial Clock
    .sync_n_x     (sync_n_x),       // SPI Frame synchronization signal (low active)
    .sync_n_x     (sync_n_x),       // SPI Frame synchronization signal (low active)
    .sync_n_y     (sync_n_y),       // SPI Frame synchronization signal (low active)
    .sync_n_y     (sync_n_y),       // SPI Frame synchronization signal (low active)
    .uart_tx      (uart_tx),        // Board UART TX pin
    .uart_tx      (dbg_uart_txd),   // Board UART TX pin
 
 
// INPUTs
// INPUTs
    .oscclk       (oscclk),         // Board Oscillator (?? MHz)
    .oscclk       (oscclk),         // Board Oscillator (?? MHz)
    .porst_n      (porst_n),        // Board Power-On reset (active low)
    .porst_n      (porst_n),        // Board Power-On reset (active low)
    .pbrst_n      (pbrst_n),        // Board Push-Button reset (active low)
    .pbrst_n      (pbrst_n),        // Board Push-Button reset (active low)
    .uart_rx      (uart_rx),        // Board UART RX pin
    .uart_rx      (dbg_uart_rxd),   // Board UART RX pin
    .switch       (switch)          // Board Switches
    .switch       (switch)          // Board Switches
);
);
 
 
 
 
//
//

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