OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 111 and 136

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 111 Rev 136
Line 57... Line 57... 
 
 
 
 
// LEDs
 
// LEDs
 
wire        [9:0] led;
 
wire        [9:0] led;
 
 
 
 
 
// UART
 
// UART
 
reg               dbg_uart_rxd;
 
wire              dbg_uart_rxd;
 
wire              dbg_uart_txd;
 
wire              dbg_uart_txd;
 
 
 
reg               dbg_uart_rxd_sel;
 
 
 
reg               dbg_uart_rxd_dly;
 
 
 
reg               dbg_uart_rxd_pre;
 
 
 
reg               dbg_uart_rxd_meta;
 
reg        [15:0] dbg_uart_buf;
 
reg        [15:0] dbg_uart_buf;
 
 
 
reg               dbg_uart_rx_busy;
 
 
 
reg               dbg_uart_tx_busy;
 
 
 
 
 
// Core debug signals
 
// Core debug signals
 
wire   [8*32-1:0] i_state;
 
wire   [8*32-1:0] i_state;
 
wire   [8*32-1:0] e_state;
 
wire   [8*32-1:0] e_state;
 
wire       [31:0] inst_cycle;
 
wire       [31:0] inst_cycle;
Line 146... Line 152... 
initial
 
initial
 
  begin
 
  begin
 
     error         = 0;
 
     error         = 0;
 
     stimulus_done = 1;
 
     stimulus_done = 1;
 
     switch        = 10'h000;
 
     switch        = 10'h000;
 
     dbg_uart_rxd  = 1'b1;
 
     dbg_uart_rxd_sel = 1'b0;
 
 
 
     dbg_uart_rxd_dly = 1'b1;
 
 
 
     dbg_uart_rxd_pre = 1'b1;
 
 
 
     dbg_uart_rxd_meta= 1'b0;
 
 
 
     dbg_uart_rx_busy = 1'b0;
 
 
 
     dbg_uart_tx_busy = 1'b0;
 
  end
 
  end
 
 
 
 
 
//
 
//
 
// openMSP430 FPGA Instance
 
// openMSP430 FPGA Instance
 
//----------------------------------
 
//----------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.