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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [dac_spi_if.v] - Diff between revs 104 and 107

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Rev 104 Rev 107
Line 54... Line 54...
// INPUTs
// INPUTs
    mclk,                           // Main system clock
    mclk,                           // Main system clock
    per_addr,                       // Peripheral address
    per_addr,                       // Peripheral address
    per_din,                        // Peripheral data input
    per_din,                        // Peripheral data input
    per_en,                         // Peripheral enable (high active)
    per_en,                         // Peripheral enable (high active)
    per_wen,                        // Peripheral write enable (high active)
    per_we,                         // Peripheral write enable (high active)
    puc                             // Main system reset
    puc                             // Main system reset
);
);
 
 
// PARAMETERs
// PARAMETERs
//============
//============
Line 78... Line 78...
//=========
//=========
input               mclk;           // Main system clock
input               mclk;           // Main system clock
input         [7:0] per_addr;       // Peripheral address
input         [7:0] per_addr;       // Peripheral address
input        [15:0] per_din;        // Peripheral data input
input        [15:0] per_din;        // Peripheral data input
input               per_en;         // Peripheral enable (high active)
input               per_en;         // Peripheral enable (high active)
input         [1:0] per_wen;        // Peripheral write enable (high active)
input         [1:0] per_we;         // Peripheral write enable (high active)
input               puc;            // Main system reset
input               puc;            // Main system reset
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  PARAMETER DECLARATION
// 1)  PARAMETER DECLARATION
Line 116... Line 116...
    CNTRL2  :     reg_dec  =  CNTRL2_D;
    CNTRL2  :     reg_dec  =  CNTRL2_D;
    default :     reg_dec  =  {512{1'b0}};
    default :     reg_dec  =  {512{1'b0}};
  endcase
  endcase
 
 
// Read/Write probes
// Read/Write probes
wire         reg_write =  |per_wen   & per_en;
wire         reg_write =  |per_we   & per_en;
wire         reg_read  = ~|per_wen   & per_en;
wire         reg_read  = ~|per_we   & per_en;
 
 
// Read/Write vectors
// Read/Write vectors
wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
wire [511:0] reg_wr    = reg_dec & {512{reg_write}};
wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
wire [511:0] reg_rd    = reg_dec & {512{reg_read}};
 
 

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