| Line 55... |
Line 55... |
mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_we, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc // Main system reset
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puc_rst // Main system reset
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);
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);
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// PARAMETERs
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// PARAMETERs
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//============
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//============
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parameter SCLK_DIV = 0; // Serial clock divider (Tsclk=Tmclk*(SCLK_DIV+1)*2)
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parameter SCLK_DIV = 0; // Serial clock divider (Tsclk=Tmclk*(SCLK_DIV+1)*2)
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| Line 75... |
Line 75... |
output sync_n; // SPI Frame synchronization signal (low active)
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output sync_n; // SPI Frame synchronization signal (low active)
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// INPUTs
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// INPUTs
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [7:0] per_addr; // Peripheral address
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input [13:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc; // Main system reset
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input puc_rst; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER DECLARATION
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// 1) PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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// Register addresses
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// Decoder bit width (defines how many bits are considered for address decoding)
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parameter DAC_VAL = BASE_ADDR;
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parameter DEC_WD = 3;
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parameter DAC_STAT = BASE_ADDR+2;
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parameter CNTRL1 = BASE_ADDR+4;
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parameter CNTRL2 = BASE_ADDR+6;
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// Register addresses offset
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parameter [DEC_WD-1:0] DAC_VAL = 'h0,
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DAC_STAT = 'h2,
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CNTRL1 = 'h4,
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CNTRL2 = 'h6;
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// Register one-hot decoder utilities
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parameter DEC_SZ = 2**DEC_WD;
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parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
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// Register one-hot decoder
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// Register one-hot decoder
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parameter DAC_VAL_D = (512'h1 << DAC_VAL);
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parameter [DEC_SZ-1:0] DAC_VAL_D = (BASE_REG << DAC_VAL),
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parameter DAC_STAT_D = (512'h1 << DAC_STAT);
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DAC_STAT_D = (BASE_REG << DAC_STAT),
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parameter CNTRL1_D = (512'h1 << CNTRL1);
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CNTRL1_D = (BASE_REG << CNTRL1),
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parameter CNTRL2_D = (512'h1 << CNTRL2);
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CNTRL2_D = (BASE_REG << CNTRL2);
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Local register selection
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wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
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// Register local address
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wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
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// Register address decode
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// Register address decode
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reg [511:0] reg_dec;
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wire [DEC_SZ-1:0] reg_dec = (DAC_VAL_D & {DEC_SZ{(reg_addr == DAC_VAL )}}) |
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always @(per_addr)
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(DAC_STAT_D & {DEC_SZ{(reg_addr == DAC_STAT)}}) |
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case ({per_addr,1'b0})
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(CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) |
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DAC_VAL : reg_dec = DAC_VAL_D;
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(CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}});
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DAC_STAT: reg_dec = DAC_STAT_D;
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CNTRL1 : reg_dec = CNTRL1_D;
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CNTRL2 : reg_dec = CNTRL2_D;
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default : reg_dec = {512{1'b0}};
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_write = |per_we & per_en;
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wire reg_write = |per_we & reg_sel;
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wire reg_read = ~|per_we & per_en;
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wire reg_read = ~|per_we & reg_sel;
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// Read/Write vectors
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// Read/Write vectors
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wire [511:0] reg_wr = reg_dec & {512{reg_write}};
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wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
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wire [511:0] reg_rd = reg_dec & {512{reg_read}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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| Line 136... |
Line 143... |
reg dac_pd0;
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reg dac_pd0;
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reg dac_pd1;
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reg dac_pd1;
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wire dac_val_wr = reg_wr[DAC_VAL];
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wire dac_val_wr = reg_wr[DAC_VAL];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc)
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if (puc_rst)
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begin
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begin
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dac_val <= 12'h000;
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dac_val <= 12'h000;
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dac_pd0 <= 1'b0;
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dac_pd0 <= 1'b0;
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dac_pd1 <= 1'b0;
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dac_pd1 <= 1'b0;
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end
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end
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| Line 157... |
Line 164... |
//------------------
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//------------------
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reg [3:0] cntrl1;
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reg [3:0] cntrl1;
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|
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wire cntrl1_wr = reg_wr[CNTRL1];
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wire cntrl1_wr = reg_wr[CNTRL1];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) cntrl1 <= 4'h0;
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if (puc_rst) cntrl1 <= 4'h0;
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else if (cntrl1_wr) cntrl1 <= per_din;
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else if (cntrl1_wr) cntrl1 <= per_din;
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// CNTRL2 Register
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// CNTRL2 Register
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//------------------
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//------------------
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reg [3:0] cntrl2;
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reg [3:0] cntrl2;
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|
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wire cntrl2_wr = reg_wr[CNTRL2];
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wire cntrl2_wr = reg_wr[CNTRL2];
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) cntrl2 <= 4'h0;
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if (puc_rst) cntrl2 <= 4'h0;
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else if (cntrl2_wr) cntrl2 <= per_din;
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else if (cntrl2_wr) cntrl2 <= per_din;
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//============================================================================
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//============================================================================
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| Line 196... |
Line 203... |
// 5) SPI INTERFACE
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// 5) SPI INTERFACE
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//============================================================================
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//============================================================================
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// SPI Clock divider
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// SPI Clock divider
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reg [3:0] spi_clk_div;
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reg [3:0] spi_clk_div;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) spi_clk_div <= SCLK_DIV;
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if (puc_rst) spi_clk_div <= SCLK_DIV;
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else if (spi_clk_div==0) spi_clk_div <= SCLK_DIV;
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else if (spi_clk_div==0) spi_clk_div <= SCLK_DIV;
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else spi_clk_div <= spi_clk_div-1;
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else spi_clk_div <= spi_clk_div-1;
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// SPI Clock generation
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// SPI Clock generation
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reg sclk;
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reg sclk;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) sclk <= 1'b0;
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if (puc_rst) sclk <= 1'b0;
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else if (spi_clk_div==0) sclk <= ~sclk;
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else if (spi_clk_div==0) sclk <= ~sclk;
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wire sclk_re = (spi_clk_div==0) & ~sclk;
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wire sclk_re = (spi_clk_div==0) & ~sclk;
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// SPI Transfer trigger
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// SPI Transfer trigger
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reg spi_tfx_trig;
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reg spi_tfx_trig;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) spi_tfx_trig <= 1'b0;
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if (puc_rst) spi_tfx_trig <= 1'b0;
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else if (dac_val_wr) spi_tfx_trig <= 1'b1;
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else if (dac_val_wr) spi_tfx_trig <= 1'b1;
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else if (sclk_re & sync_n) spi_tfx_trig <= 1'b0;
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else if (sclk_re & sync_n) spi_tfx_trig <= 1'b0;
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wire spi_tfx_init = spi_tfx_trig & sync_n;
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wire spi_tfx_init = spi_tfx_trig & sync_n;
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// Data counter
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// Data counter
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reg [3:0] spi_cnt;
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reg [3:0] spi_cnt;
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wire spi_cnt_done = (spi_cnt==4'hf);
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wire spi_cnt_done = (spi_cnt==4'hf);
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) spi_cnt <= 4'hf;
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if (puc_rst) spi_cnt <= 4'hf;
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else if (sclk_re)
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else if (sclk_re)
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if (spi_tfx_init) spi_cnt <= 4'he;
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if (spi_tfx_init) spi_cnt <= 4'he;
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else if (~spi_cnt_done) spi_cnt <= spi_cnt-1;
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else if (~spi_cnt_done) spi_cnt <= spi_cnt-1;
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|
|
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// Frame synchronization signal (low active)
|
// Frame synchronization signal (low active)
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reg sync_n;
|
reg sync_n;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) sync_n <= 1'b1;
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if (puc_rst) sync_n <= 1'b1;
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else if (sclk_re)
|
else if (sclk_re)
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if (spi_tfx_init) sync_n <= 1'b0;
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if (spi_tfx_init) sync_n <= 1'b0;
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else if (spi_cnt_done) sync_n <= 1'b1;
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else if (spi_cnt_done) sync_n <= 1'b1;
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|
|
|
|
// Value to be shifted_out
|
// Value to be shifted_out
|
reg [15:0] dac_shifter;
|
reg [15:0] dac_shifter;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) dac_shifter <= 16'h000;
|
if (puc_rst) dac_shifter <= 16'h000;
|
else if (sclk_re)
|
else if (sclk_re)
|
if (spi_tfx_init) dac_shifter <= {2'b00, dac_pd1, dac_pd0, dac_val[11:0]};
|
if (spi_tfx_init) dac_shifter <= {2'b00, dac_pd1, dac_pd0, dac_val[11:0]};
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else dac_shifter <= {dac_shifter[14:0], 1'b0};
|
else dac_shifter <= {dac_shifter[14:0], 1'b0};
|
|
|
assign din = dac_shifter[15];
|
assign din = dac_shifter[15];
|
