| Line 95... |
Line 95... |
wire [15:0] pmem_dout;
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wire [15:0] pmem_dout;
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wire [7:0] per_addr;
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wire [7:0] per_addr;
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wire [15:0] per_din;
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wire [15:0] per_din;
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wire per_en;
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wire per_en;
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wire [1:0] per_wen;
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wire [1:0] per_we;
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wire [15:0] per_dout;
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wire [15:0] per_dout;
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wire [13:0] irq_acc;
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wire [13:0] irq_acc;
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wire [13:0] irq_bus;
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wire [13:0] irq_bus;
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wire lfxt_clk;
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wire lfxt_clk;
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| Line 313... |
Line 313... |
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.dmem_wen (dmem_wen), // Data Memory write enable (low active)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.puc (puc), // Main system reset
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.puc (puc), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable
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.smclk_en (smclk_en), // SMCLK enable
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// INPUTs
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// INPUTs
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.cpu_en (1'b1), // Enable CPU code execution (asynchronous)
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.dbg_en (1'b1), // Debug interface enable (asynchronous)
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.dbg_uart_rxd (uart_rx), // Debug interface: UART RXD
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.dbg_uart_rxd (uart_rx), // Debug interface: UART RXD
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dco_clk (dco_clk), // Fast oscillator (fast clock)
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.dmem_dout (dmem_dout), // Data Memory data output
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.dmem_dout (dmem_dout), // Data Memory data output
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.irq (irq_bus), // Maskable interrupts
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.irq (irq_bus), // Maskable interrupts
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)
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| Line 358... |
Line 360... |
// INPUTs
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// INPUTs
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc (puc) // Main system reset
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);
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);
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|
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dac_spi_if #(1, 9'h1A0) dac_spi_if_y (
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dac_spi_if #(1, 9'h1A0) dac_spi_if_y (
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|
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| Line 377... |
Line 379... |
// INPUTs
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// INPUTs
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc (puc) // Main system reset
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);
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);
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|
|
//
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//
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// Digital I/O
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// Digital I/O
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| Line 426... |
Line 428... |
.p5_din (8'h00), // Port 5 data input
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.p5_din (8'h00), // Port 5 data input
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.p6_din (8'h00), // Port 6 data input
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.p6_din (8'h00), // Port 6 data input
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc (puc) // Main system reset
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);
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);
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|
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//
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//
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// Timer A
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// Timer A
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| Line 456... |
Line 458... |
.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
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.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_wen (per_wen), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc), // Main system reset
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.puc (puc), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable (from CPU)
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.smclk_en (smclk_en), // SMCLK enable (from CPU)
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.ta_cci0a (1'b0), // Timer A capture 0 input A
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.ta_cci0a (1'b0), // Timer A capture 0 input A
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.ta_cci0b (1'b0), // Timer A capture 0 input B
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.ta_cci0b (1'b0), // Timer A capture 0 input B
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.ta_cci1a (1'b0), // Timer A capture 1 input A
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.ta_cci1a (1'b0), // Timer A capture 1 input A
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