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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openMSP430_fpga.v] - Diff between revs 107 and 111

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Rev 107 Rev 111
Line 92... Line 92... 
wire                pmem_cen;
 
wire                pmem_cen;
 
wire         [15:0] pmem_din;
 
wire         [15:0] pmem_din;
 
wire          [1:0] pmem_wen;
 
wire          [1:0] pmem_wen;
 
wire         [15:0] pmem_dout;
 
wire         [15:0] pmem_dout;
 
 
 
 
 
wire          [7:0] per_addr;
 
wire         [13:0] per_addr;
 
wire         [15:0] per_din;
 
wire         [15:0] per_din;
 
wire                per_en;
 
wire                per_en;
 
wire          [1:0] per_we;
 
wire          [1:0] per_we;
 
wire         [15:0] per_dout;
 
wire         [15:0] per_dout;
 
 
 
 
Line 106... Line 106... 
wire                nmi;
 
wire                nmi;
 
wire                reset_n;
 
wire                reset_n;
 
 
 
 
 
wire                dco_clk;
 
wire                dco_clk;
 
wire                mclk;
 
wire                mclk;
 
wire                puc;
 
wire                puc_rst;
 
 
 
 
 
wire          [7:0] p1_din;
 
wire          [7:0] p1_din;
 
wire          [7:0] p1_dout;
 
wire          [7:0] p1_dout;
 
wire          [7:0] p1_dout_en;
 
wire          [7:0] p1_dout_en;
 
wire          [7:0] p1_sel;
 
wire          [7:0] p1_sel;
Line 288... Line 288... 
 
 
 
 
//=============================================================================
 
//=============================================================================
 
// 3)  PROGRAM AND DATA MEMORIES
 
// 3)  PROGRAM AND DATA MEMORIES
 
//=============================================================================
 
//=============================================================================
 
 
 
 
 
dmem_128B dmem_hi (.WD(dmem_din[15:8]), .RD(dmem_dout[15:8]), .WEN(dmem_wen[1] | dmem_cen), .REN(~dmem_wen[1] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc));
 
dmem_128B dmem_hi (.WD(dmem_din[15:8]), .RD(dmem_dout[15:8]), .WEN(dmem_wen[1] | dmem_cen), .REN(~dmem_wen[1] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
 
dmem_128B dmem_lo (.WD(dmem_din[7:0]),  .RD(dmem_dout[7:0]),  .WEN(dmem_wen[0] | dmem_cen), .REN(~dmem_wen[0] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc));
 
dmem_128B dmem_lo (.WD(dmem_din[7:0]),  .RD(dmem_dout[7:0]),  .WEN(dmem_wen[0] | dmem_cen), .REN(~dmem_wen[0] | dmem_cen), .WADDR(dmem_addr) , .RADDR(dmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
 
 
 
 
 
pmem_2kB  pmem_hi (.WD(pmem_din[15:8]), .RD(pmem_dout[15:8]), .WEN(pmem_wen[1] | pmem_cen), .REN(~pmem_wen[1] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc));
 
pmem_2kB  pmem_hi (.WD(pmem_din[15:8]), .RD(pmem_dout[15:8]), .WEN(pmem_wen[1] | pmem_cen), .REN(~pmem_wen[1] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
 
pmem_2kB  pmem_lo (.WD(pmem_din[7:0]),  .RD(pmem_dout[7:0]),  .WEN(pmem_wen[0] | pmem_cen), .REN(~pmem_wen[0] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc));
 
pmem_2kB  pmem_lo (.WD(pmem_din[7:0]),  .RD(pmem_dout[7:0]),  .WEN(pmem_wen[0] | pmem_cen), .REN(~pmem_wen[0] | pmem_cen), .WADDR(pmem_addr) , .RADDR(pmem_addr), .RWCLK(mclk), .RESET(~puc_rst));
 
 
 
 
 
 
 
 
 
//=============================================================================
 
//=============================================================================
 
// 4)  OPENMSP430
 
// 4)  OPENMSP430
 
//=============================================================================
 
//=============================================================================
Line 319... Line 319... 
    .per_en       (per_en),       // Peripheral enable (high active)
 
    .per_en       (per_en),       // Peripheral enable (high active)
 
    .pmem_addr    (pmem_addr),    // Program Memory address
 
    .pmem_addr    (pmem_addr),    // Program Memory address
 
    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)
 
    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)
 
    .pmem_din     (pmem_din),     // Program Memory data input (optional)
 
    .pmem_din     (pmem_din),     // Program Memory data input (optional)
 
    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)
 
    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)
 
    .puc          (puc),          // Main system reset
 
    .puc_rst      (puc_rst),      // Main system reset
 
    .smclk_en     (smclk_en),     // SMCLK enable
 
    .smclk_en     (smclk_en),     // SMCLK enable
 
 
 
 
 
// INPUTs
 
// INPUTs
 
    .cpu_en       (1'b1),         // Enable CPU code execution (asynchronous)
 
    .cpu_en       (1'b1),         // Enable CPU code execution (asynchronous)
 
    .dbg_en       (1'b1),         // Debug interface enable (asynchronous)
 
    .dbg_en       (1'b1),         // Debug interface enable (asynchronous)
Line 361... Line 361... 
    .mclk         (mclk),           // Main system clock
 
    .mclk         (mclk),           // Main system clock
 
    .per_addr     (per_addr),       // Peripheral address
 
    .per_addr     (per_addr),       // Peripheral address
 
    .per_din      (per_din),        // Peripheral data input
 
    .per_din      (per_din),        // Peripheral data input
 
    .per_en       (per_en),         // Peripheral enable (high active)
 
    .per_en       (per_en),         // Peripheral enable (high active)
 
    .per_we       (per_we),         // Peripheral write enable (high active)
 
    .per_we       (per_we),         // Peripheral write enable (high active)
 
    .puc          (puc)             // Main system reset
 
    .puc_rst      (puc_rst)         // Main system reset
 
);
 
);
 
 
 
 
 
dac_spi_if #(1, 9'h1A0) dac_spi_if_y (
 
dac_spi_if #(1, 9'h1A0) dac_spi_if_y (
 
 
 
 
 
// OUTPUTs
 
// OUTPUTs
Line 380... Line 380... 
    .mclk         (mclk),           // Main system clock
 
    .mclk         (mclk),           // Main system clock
 
    .per_addr     (per_addr),       // Peripheral address
 
    .per_addr     (per_addr),       // Peripheral address
 
    .per_din      (per_din),        // Peripheral data input
 
    .per_din      (per_din),        // Peripheral data input
 
    .per_en       (per_en),         // Peripheral enable (high active)
 
    .per_en       (per_en),         // Peripheral enable (high active)
 
    .per_we       (per_we),         // Peripheral write enable (high active)
 
    .per_we       (per_we),         // Peripheral write enable (high active)
 
    .puc          (puc)             // Main system reset
 
    .puc_rst      (puc_rst)         // Main system reset
 
);
 
);
 
 
 
 
 
//
 
//
 
// Digital I/O
 
// Digital I/O
 
//-------------------------------
 
//-------------------------------
Line 429... Line 429... 
    .p6_din       (8'h00),         // Port 6 data input
 
    .p6_din       (8'h00),         // Port 6 data input
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .puc          (puc)            // Main system reset
 
    .puc_rst      (puc_rst)        // Main system reset
 
);
 
);
 
 
 
 
 
//
 
//
 
// Timer A
 
// Timer A
 
//----------------------------------------------
 
//----------------------------------------------
Line 459... Line 459... 
    .mclk         (mclk),          // Main system clock
 
    .mclk         (mclk),          // Main system clock
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_addr     (per_addr),      // Peripheral address
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_din      (per_din),       // Peripheral data input
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
    .puc          (puc),           // Main system reset
 
    .puc_rst      (puc_rst),       // Main system reset
 
    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)
 
    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)
 
    .ta_cci0a     (1'b0),          // Timer A capture 0 input A
 
    .ta_cci0a     (1'b0),          // Timer A capture 0 input A
 
    .ta_cci0b     (1'b0),          // Timer A capture 0 input B
 
    .ta_cci0b     (1'b0),          // Timer A capture 0 input B
 
    .ta_cci1a     (1'b0),          // Timer A capture 1 input A
 
    .ta_cci1a     (1'b0),          // Timer A capture 1 input A
 
    .ta_cci1b     (1'b0),          // Timer A capture 1 input B
 
    .ta_cci1b     (1'b0),          // Timer A capture 1 input B

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