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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openMSP430_fpga.v] - Diff between revs 81 and 82

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Rev 81 Rev 82
Line 271... Line 271...
//             |   Min.  Max.  |   Min.  Max.  |   Min.  Max. |   Min.  Max.  |
//             |   Min.  Max.  |   Min.  Max.  |   Min.  Max. |   Min.  Max.  |
//             |  (MHz) (MHz)  |  (MHz) (MHz)  |  (MHz) (MHz) |  (MHz) (MHz)  |
//             |  (MHz) (MHz)  |  (MHz) (MHz)  |  (MHz) (MHz) |  (MHz) (MHz)  |
//-------------+---------------+---------------+--------------+---------------|
//-------------+---------------+---------------+--------------+---------------|
// IGLOO and IGLOO PLUS                                                       |
// IGLOO and IGLOO PLUS                                                       |
//-------------+---------------+---------------+--------------+---------------|
//-------------+---------------+---------------+--------------+---------------|
// 1.2 V ± 5%  |   24    35    |   30     70   |   60    140  |   135   160   |
// 1.2 V +- 5% |   24    35    |   30     70   |   60    140  |   135   160   |
// 1.5 V ± 5%  |   24    43.75 |   30     87.5 |   60    175  |   135   250   |
// 1.5 V +- 5% |   24    43.75 |   30     87.5 |   60    175  |   135   250   |
//-------------+---------------+---------------+--------------+---------------|
//-------------+---------------+---------------+--------------+---------------|
// ProASIC3L, RT ProASIC3, and Military ProASIC3/L                            |
// ProASIC3L, RT ProASIC3, and Military ProASIC3/L                            |
//-------------+---------------+---------------+--------------+---------------|
//-------------+---------------+---------------+--------------+---------------|
// 1.2 V ± 5%  |   24    35    |    30    70   |   60    140  |   135   250   |
// 1.2 V +- 5% |   24    35    |    30    70   |   60    140  |   135   250   |
// 1.5 V ± 5%  |   24    43.75 |    30    70   |   60    175  |   135   350   |
// 1.5 V +- 5% |   24    43.75 |    30    70   |   60    175  |   135   350   |
//-------------+---------------+---------------+--------------+---------------|
//-------------+---------------+---------------+--------------+---------------|
// ProASIC3 and Fusion                                                        |
// ProASIC3 and Fusion                                                        |
//-------------+---------------+---------------+--------------+---------------|
//-------------+---------------+---------------+--------------+---------------|
// 1.5 V ± 5%  |   24    43.75 |    33.75 87.5 |  67.5   175  |   135   350   |
// 1.5 V +- 5% |   24    43.75 |    33.75 87.5 |  67.5   175  |   135   350   |
//-------------+---------------+---------------+--------------+---------------+
//-------------+---------------+---------------+--------------+---------------+
 
 
 
 
//=============================================================================
//=============================================================================
// 3)  PROGRAM AND DATA MEMORIES
// 3)  PROGRAM AND DATA MEMORIES
Line 506... Line 506...
 
 
assign  reset_n =  (porst_n & pbrst_n);
assign  reset_n =  (porst_n & pbrst_n);
 
 
assign  p1_din  =  8'h00;
assign  p1_din  =  8'h00;
 
 
assign  led     =  {cntrl1, p1_dout, p1_dout, cntrl2};
assign  led     =  {cntrl1, p1_dout[0], p1_dout[0], cntrl2};
 
 
 
 
endmodule // openMSP430_fpga
endmodule // openMSP430_fpga
 
 
 
 
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