URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_alu.v] - Diff between revs 104 and 111

Rev 104	Rev 111
Line 90...	Line 90...
`input [3:0] Y;`	`input [3:0] Y;`
`input C;`	`input C;`

`reg [4:0] Z;`	`reg [4:0] Z;`
`begin`	`begin`
`Z = {1'b0,X}+{1'b0,Y}+C;`	`Z = {1'b0,X}+{1'b0,Y}+{4'b0,C};`
`if (Z<10) bcd_add = Z;`	`if (Z<5'd10) bcd_add = Z;`
`else bcd_add = Z+6;`	`else bcd_add = Z+5'd6;`
`end`	`end`

`endfunction`	`endfunction`


Line 202...	Line 202...
inst_alu[`ALU_XOR] \|	inst_alu[`ALU_XOR] \|
inst_alu[`ALU_SHIFT] \|	inst_alu[`ALU_SHIFT] \|
inst_so[`SWPB] \|	inst_so[`SWPB] \|
inst_so[`SXT]);	inst_so[`SXT]);

wire [16:0] alu_short = ({16{inst_alu[`ALU_AND]}} & alu_and) \|	wire [16:0] alu_short = ({17{inst_alu[`ALU_AND]}} & alu_and) \|
({16{inst_alu[`ALU_OR]}} & alu_or) \|	({17{inst_alu[`ALU_OR]}} & alu_or) \|
({16{inst_alu[`ALU_XOR]}} & alu_xor) \|	({17{inst_alu[`ALU_XOR]}} & alu_xor) \|
({16{inst_alu[`ALU_SHIFT]}} & alu_shift) \|	({17{inst_alu[`ALU_SHIFT]}} & alu_shift) \|
({16{inst_so[`SWPB]}} & alu_swpb) \|	({17{inst_so[`SWPB]}} & alu_swpb) \|
({16{inst_so[`SXT]}} & alu_sxt) \|	({17{inst_so[`SXT]}} & alu_sxt) \|
`({16{alu_short_thro}} & op_src_in);`	`({17{alu_short_thro}} & op_src_in);`


`// ALU output mux`	`// ALU output mux`
wire [16:0] alu_out_nxt = (inst_so[`IRQ] \| dbg_halt_st \|	wire [16:0] alu_out_nxt = (inst_so[`IRQ] \| dbg_halt_st \|
inst_alu[`ALU_ADD]) ? alu_add_inc :	inst_alu[`ALU_ADD]) ? alu_add_inc :