| Line 119... |
Line 119... |
reg in1_select_ss;
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reg in1_select_ss;
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wire in1_enable;
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wire in1_enable;
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wire clk_in0_inv;
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wire clk_in0_inv;
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wire clk_in1_inv;
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wire clk_in1_inv;
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wire clk_in0_scan_fix_inv;
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wire clk_in1_scan_fix_inv;
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wire gated_clk_in0;
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wire gated_clk_in0;
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wire gated_clk_in1;
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wire gated_clk_in1;
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//-----------------------------------------------------------------------------
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// Optional scan repair for neg-edge clocked FF
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//-----------------------------------------------------------------------------
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`ifdef SCAN_REPAIR_INV_CLOCKS
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omsp_scan_mux scan_mux_repair_clk_in0_inv (.scan_mode(scan_mode), .data_in_scan(clk_in0), .data_in_func(~clk_in0), .data_out(clk_in0_scan_fix_inv));
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omsp_scan_mux scan_mux_repair_clk_in1_inv (.scan_mode(scan_mode), .data_in_scan(clk_in1), .data_in_func(~clk_in1), .data_out(clk_in1_scan_fix_inv));
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`else
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assign clk_in0_scan_fix_inv = ~clk_in0;
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assign clk_in1_scan_fix_inv = ~clk_in1;
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`endif
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// CLK_IN0 Selection
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// CLK_IN0 Selection
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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assign in0_select = ~select_in & ~in1_select_ss;
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assign in0_select = ~select_in & ~in1_select_ss;
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always @ (posedge clk_in0_inv or posedge reset)
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always @ (posedge clk_in0_scan_fix_inv or posedge reset)
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if (reset) in0_select_s <= 1'b1;
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if (reset) in0_select_s <= 1'b1;
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else in0_select_s <= in0_select;
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else in0_select_s <= in0_select;
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always @ (posedge clk_in0 or posedge reset)
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always @ (posedge clk_in0 or posedge reset)
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if (reset) in0_select_ss <= 1'b1;
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if (reset) in0_select_ss <= 1'b1;
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| Line 146... |
Line 158... |
// CLK_IN1 Selection
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// CLK_IN1 Selection
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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assign in1_select = select_in & ~in0_select_ss;
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assign in1_select = select_in & ~in0_select_ss;
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always @ (posedge clk_in1_inv or posedge reset)
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always @ (posedge clk_in1_scan_fix_inv or posedge reset)
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if (reset) in1_select_s <= 1'b0;
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if (reset) in1_select_s <= 1'b0;
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else in1_select_s <= in1_select;
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else in1_select_s <= in1_select;
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always @ (posedge clk_in1 or posedge reset)
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always @ (posedge clk_in1 or posedge reset)
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if (reset) in1_select_ss <= 1'b0;
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if (reset) in1_select_ss <= 1'b0;
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| Line 173... |
Line 185... |
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// Replace with standard cell INVERTER
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// Replace with standard cell INVERTER
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assign clk_in0_inv = ~clk_in0;
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assign clk_in0_inv = ~clk_in0;
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assign clk_in1_inv = ~clk_in1;
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assign clk_in1_inv = ~clk_in1;
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// Replace with standard cell NAND2
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// Replace with standard cell NAND2
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assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
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assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
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assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
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assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
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