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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_clock_mux.v] - Diff between revs 202 and 205

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Rev 202 Rev 205
Line 119... Line 119...
reg  in1_select_ss;
reg  in1_select_ss;
wire in1_enable;
wire in1_enable;
 
 
wire clk_in0_inv;
wire clk_in0_inv;
wire clk_in1_inv;
wire clk_in1_inv;
 
wire clk_in0_scan_fix_inv;
 
wire clk_in1_scan_fix_inv;
wire gated_clk_in0;
wire gated_clk_in0;
wire gated_clk_in1;
wire gated_clk_in1;
 
 
 
//-----------------------------------------------------------------------------
 
// Optional scan repair for neg-edge clocked FF
 
//-----------------------------------------------------------------------------
 
`ifdef SCAN_REPAIR_INV_CLOCKS
 
   omsp_scan_mux scan_mux_repair_clk_in0_inv (.scan_mode(scan_mode), .data_in_scan(clk_in0), .data_in_func(~clk_in0), .data_out(clk_in0_scan_fix_inv));
 
   omsp_scan_mux scan_mux_repair_clk_in1_inv (.scan_mode(scan_mode), .data_in_scan(clk_in1), .data_in_func(~clk_in1), .data_out(clk_in1_scan_fix_inv));
 
`else
 
   assign clk_in0_scan_fix_inv = ~clk_in0;
 
   assign clk_in1_scan_fix_inv = ~clk_in1;
 
`endif
 
 
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
// CLK_IN0 Selection
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
 
 
assign in0_select = ~select_in & ~in1_select_ss;
assign in0_select = ~select_in & ~in1_select_ss;
 
 
always @ (posedge clk_in0_inv or posedge reset)
always @ (posedge clk_in0_scan_fix_inv or posedge reset)
  if (reset) in0_select_s  <=  1'b1;
  if (reset) in0_select_s  <=  1'b1;
  else       in0_select_s  <=  in0_select;
  else       in0_select_s  <=  in0_select;
 
 
always @ (posedge clk_in0     or posedge reset)
always @ (posedge clk_in0     or posedge reset)
  if (reset) in0_select_ss <=  1'b1;
  if (reset) in0_select_ss <=  1'b1;
Line 146... Line 158...
// CLK_IN1 Selection
// CLK_IN1 Selection
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
 
 
assign in1_select =  select_in & ~in0_select_ss;
assign in1_select =  select_in & ~in0_select_ss;
 
 
always @ (posedge clk_in1_inv or posedge reset)
always @ (posedge clk_in1_scan_fix_inv or posedge reset)
  if (reset) in1_select_s  <=  1'b0;
  if (reset) in1_select_s  <=  1'b0;
  else       in1_select_s  <=  in1_select;
  else       in1_select_s  <=  in1_select;
 
 
always @ (posedge clk_in1     or posedge reset)
always @ (posedge clk_in1     or posedge reset)
  if (reset) in1_select_ss <=  1'b0;
  if (reset) in1_select_ss <=  1'b0;
Line 173... Line 185...
 
 
// Replace with standard cell INVERTER
// Replace with standard cell INVERTER
assign clk_in0_inv   = ~clk_in0;
assign clk_in0_inv   = ~clk_in0;
assign clk_in1_inv   = ~clk_in1;
assign clk_in1_inv   = ~clk_in1;
 
 
 
 
// Replace with standard cell NAND2
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
 
 
 
 

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