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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg.v] - Diff between revs 107 and 111

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Rev 107 Rev 111
Line 29... Line 29...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 106 $
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
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    eu_mdb_out,                     // Memory data bus output
    eu_mdb_out,                     // Memory data bus output
    exec_done,                      // Execution completed
    exec_done,                      // Execution completed
    fe_mb_en,                       // Frontend Memory bus enable
    fe_mb_en,                       // Frontend Memory bus enable
    fe_mdb_in,                      // Frontend Memory data bus input
    fe_mdb_in,                      // Frontend Memory data bus input
    pc,                             // Program counter
    pc,                             // Program counter
    puc                             // Main system reset
    puc_rst                         // Main system reset
);
);
 
 
// OUTPUTs
// OUTPUTs
//=========
//=========
output              dbg_freeze;     // Freeze peripherals
output              dbg_freeze;     // Freeze peripherals
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input        [15:0] eu_mdb_out;     // Memory data bus output
input        [15:0] eu_mdb_out;     // Memory data bus output
input               exec_done;      // Execution completed
input               exec_done;      // Execution completed
input               fe_mb_en;       // Frontend Memory bus enable
input               fe_mb_en;       // Frontend Memory bus enable
input        [15:0] fe_mdb_in;      // Frontend Memory data bus input
input        [15:0] fe_mdb_in;      // Frontend Memory data bus input
input        [15:0] pc;             // Program counter
input        [15:0] pc;             // Program counter
input               puc;            // Main system reset
input               puc_rst;        // Main system reset
 
 
 
 
//=============================================================================
//=============================================================================
// 1)  WIRE & PARAMETER DECLARATION
// 1)  WIRE & PARAMETER DECLARATION
//=============================================================================
//=============================================================================
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// PUC is localy used as a data.
// PUC is localy used as a data.
reg  [1:0] puc_sync;
reg  [1:0] puc_sync;
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst) puc_sync <=  2'b11;
  if (dbg_rst) puc_sync <=  2'b11;
  else         puc_sync <=  {puc_sync[0] , puc};
  else         puc_sync <=  {puc_sync[0] , puc_rst};
wire           puc_s     =  puc_sync[1];
wire           puc_s     =  puc_sync[1];
 
 
 
 
//============================================================================
//============================================================================
// 2)  REGISTER DECODER
// 2)  REGISTER DECODER
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// 3)  REGISTER: CORE INTERFACE
// 3)  REGISTER: CORE INTERFACE
//=============================================================================
//=============================================================================
 
 
// CPU_ID Register
// CPU_ID Register
//-----------------   
//-----------------   
 
//              -------------------------------------------------------------------
 
// CPU_ID_LO:  | 15  14  13  12  11  10  9  |  8  7  6  5  4  |  3   |   2  1  0   |
 
//             |----------------------------+-----------------+------+-------------|
 
//             |        PER_SPACE           |   USER_VERSION  | ASIC | CPU_VERSION |
 
//              --------------------------------------------------------------------
 
// CPU_ID_HI:  |   15  14  13  12  11  10   |   9  8  7  6  5  4  3  2  1   |   0  |
 
//             |----------------------------+-------------------------------+------|
 
//             |         PMEM_SIZE          |            DMEM_SIZE          |  MPY |
 
//              -------------------------------------------------------------------
 
 
 
wire  [2:0] cpu_version  =  `CPU_VERSION;
 
`ifdef ASIC
 
wire        cpu_asic     =  1'b1;
 
`else
 
wire        cpu_asic     =  1'b0;
 
`endif
 
wire  [4:0] user_version =  `USER_VERSION;
 
wire  [6:0] per_space    = (`PER_SIZE  >> 9);  // cpu_id_per  *  512 = peripheral space size
 
`ifdef MULTIPLIER
 
wire        mpy_info     =  1'b1;
 
`else
 
wire        mpy_info     =  1'b0;
 
`endif
 
wire  [8:0] dmem_size    = (`DMEM_SIZE >> 7);  // cpu_id_dmem *  128 = data memory size
 
wire  [5:0] pmem_size    = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size
 
 
wire [15:0] cpu_id_pmem = `PMEM_SIZE;
wire [31:0] cpu_id       = {pmem_size,
wire [15:0] cpu_id_dmem = `DMEM_SIZE;
                            dmem_size,
wire [31:0] cpu_id      = {cpu_id_pmem, cpu_id_dmem};
                            mpy_info,
 
                            per_space,
 
                            user_version,
 
                            cpu_asic,
 
                            cpu_version};
 
 
 
 
// CPU_CTL Register
// CPU_CTL Register
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
//       7         6          5          4           3        2     1    0
//       7         6          5          4           3        2     1    0

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