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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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// Copyright (C) 2009 , Olivier Girard
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//
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//
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// This source file may be used and distributed without restriction provided
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// Redistribution and use in source and binary forms, with or without
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// that this copyright statement is not removed from the file and that any
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// modification, are permitted provided that the following conditions
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// derivative work contains the original copyright notice and the associated
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// are met:
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// disclaimer.
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// * Redistributions of source code must retain the above copyright
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//
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// notice, this list of conditions and the following disclaimer.
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// This source file is free software; you can redistribute it and/or modify
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// * Redistributions in binary form must reproduce the above copyright
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// it under the terms of the GNU Lesser General Public License as published
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// notice, this list of conditions and the following disclaimer in the
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// by the Free Software Foundation; either version 2.1 of the License, or
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// documentation and/or other materials provided with the distribution.
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// (at your option) any later version.
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// * Neither the name of the authors nor the names of its contributors
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//
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// may be used to endorse or promote products derived from this software
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// without specific prior written permission.
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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//
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// License for more details.
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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//
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// You should have received a copy of the GNU Lesser General Public License
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// along with this source; if not, write to the Free Software Foundation,
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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// THE POSSIBILITY OF SUCH DAMAGE
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//
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//
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// *File Name: omsp_dbg.v
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// *File Name: omsp_dbg.v
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//
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//
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| Line 53... |
Line 58... |
dbg_cpu_reset, // Reset CPU from debug interface
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dbg_cpu_reset, // Reset CPU from debug interface
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dbg_uart_txd, // Debug interface: UART TXD
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dbg_uart_txd, // Debug interface: UART TXD
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// INPUTs
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// INPUTs
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cpu_en_s, // Enable CPU code execution (synchronous)
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cpu_en_s, // Enable CPU code execution (synchronous)
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cpu_id, // CPU ID
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dbg_clk, // Debug unit clock
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dbg_clk, // Debug unit clock
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dbg_en_s, // Debug interface enable (synchronous)
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dbg_en_s, // Debug interface enable (synchronous)
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dbg_halt_st, // Halt/Run status from CPU
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dbg_halt_st, // Halt/Run status from CPU
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dbg_mem_din, // Debug unit Memory data input
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dbg_mem_din, // Debug unit Memory data input
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dbg_reg_din, // Debug unit CPU register data input
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dbg_reg_din, // Debug unit CPU register data input
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| Line 70... |
Line 76... |
eu_mdb_out, // Memory data bus output
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eu_mdb_out, // Memory data bus output
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exec_done, // Execution completed
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exec_done, // Execution completed
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fe_mb_en, // Frontend Memory bus enable
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fe_mb_en, // Frontend Memory bus enable
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fe_mdb_in, // Frontend Memory data bus input
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fe_mdb_in, // Frontend Memory data bus input
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pc, // Program counter
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pc, // Program counter
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puc_rst // Main system reset
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puc_pnd_set // PUC pending set for the serial debug interface
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output dbg_freeze; // Freeze peripherals
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output dbg_freeze; // Freeze peripherals
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| Line 88... |
Line 94... |
output dbg_uart_txd; // Debug interface: UART TXD
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output dbg_uart_txd; // Debug interface: UART TXD
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// INPUTs
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// INPUTs
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//=========
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//=========
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input cpu_en_s; // Enable CPU code execution (synchronous)
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input cpu_en_s; // Enable CPU code execution (synchronous)
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input [31:0] cpu_id; // CPU ID
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input dbg_clk; // Debug unit clock
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input dbg_clk; // Debug unit clock
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input dbg_en_s; // Debug interface enable (synchronous)
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input dbg_en_s; // Debug interface enable (synchronous)
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input dbg_halt_st; // Halt/Run status from CPU
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input dbg_halt_st; // Halt/Run status from CPU
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input [15:0] dbg_mem_din; // Debug unit Memory data input
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input [15:0] dbg_mem_din; // Debug unit Memory data input
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input [15:0] dbg_reg_din; // Debug unit CPU register data input
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input [15:0] dbg_reg_din; // Debug unit CPU register data input
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| Line 105... |
Line 112... |
input [15:0] eu_mdb_out; // Memory data bus output
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input [15:0] eu_mdb_out; // Memory data bus output
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input exec_done; // Execution completed
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input exec_done; // Execution completed
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input fe_mb_en; // Frontend Memory bus enable
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input fe_mb_en; // Frontend Memory bus enable
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input [15:0] fe_mdb_in; // Frontend Memory data bus input
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input [15:0] fe_mdb_in; // Frontend Memory data bus input
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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input puc_rst; // Main system reset
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input puc_pnd_set; // PUC pending set for the serial debug interface
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//=============================================================================
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//=============================================================================
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// 1) WIRE & PARAMETER DECLARATION
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// 1) WIRE & PARAMETER DECLARATION
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//=============================================================================
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//=============================================================================
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| Line 138... |
Line 145... |
wire [15:0] brk2_dout;
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wire [15:0] brk2_dout;
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wire brk3_halt;
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wire brk3_halt;
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wire brk3_pnd;
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wire brk3_pnd;
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wire [15:0] brk3_dout;
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wire [15:0] brk3_dout;
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// Number of registers
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parameter NR_REG = 24;
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// Register addresses
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// Register addresses
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parameter CPU_ID_LO = 6'h00;
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parameter CPU_ID_LO = 6'h00;
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parameter CPU_ID_HI = 6'h01;
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parameter CPU_ID_HI = 6'h01;
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parameter CPU_CTL = 6'h02;
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parameter CPU_CTL = 6'h02;
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parameter CPU_STAT = 6'h03;
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parameter CPU_STAT = 6'h03;
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Line 183... |
parameter BRK3_ADDR0 = 6'h16;
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parameter BRK3_ADDR0 = 6'h16;
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parameter BRK3_ADDR1 = 6'h17;
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parameter BRK3_ADDR1 = 6'h17;
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`endif
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`endif
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// Register one-hot decoder
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// Register one-hot decoder
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parameter CPU_ID_LO_D = (64'h1 << CPU_ID_LO);
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parameter BASE_D = {{NR_REG-1{1'b0}}, 1'b1};
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parameter CPU_ID_HI_D = (64'h1 << CPU_ID_HI);
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parameter CPU_ID_LO_D = (BASE_D << CPU_ID_LO);
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parameter CPU_CTL_D = (64'h1 << CPU_CTL);
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parameter CPU_ID_HI_D = (BASE_D << CPU_ID_HI);
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parameter CPU_STAT_D = (64'h1 << CPU_STAT);
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parameter CPU_CTL_D = (BASE_D << CPU_CTL);
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parameter MEM_CTL_D = (64'h1 << MEM_CTL);
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parameter CPU_STAT_D = (BASE_D << CPU_STAT);
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parameter MEM_ADDR_D = (64'h1 << MEM_ADDR);
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parameter MEM_CTL_D = (BASE_D << MEM_CTL);
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parameter MEM_DATA_D = (64'h1 << MEM_DATA);
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parameter MEM_ADDR_D = (BASE_D << MEM_ADDR);
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parameter MEM_CNT_D = (64'h1 << MEM_CNT);
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parameter MEM_DATA_D = (BASE_D << MEM_DATA);
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parameter MEM_CNT_D = (BASE_D << MEM_CNT);
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`ifdef DBG_HWBRK_0
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`ifdef DBG_HWBRK_0
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parameter BRK0_CTL_D = (64'h1 << BRK0_CTL);
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parameter BRK0_CTL_D = (BASE_D << BRK0_CTL);
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parameter BRK0_STAT_D = (64'h1 << BRK0_STAT);
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parameter BRK0_STAT_D = (BASE_D << BRK0_STAT);
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parameter BRK0_ADDR0_D = (64'h1 << BRK0_ADDR0);
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parameter BRK0_ADDR0_D = (BASE_D << BRK0_ADDR0);
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parameter BRK0_ADDR1_D = (64'h1 << BRK0_ADDR1);
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parameter BRK0_ADDR1_D = (BASE_D << BRK0_ADDR1);
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`endif
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`endif
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`ifdef DBG_HWBRK_1
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`ifdef DBG_HWBRK_1
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parameter BRK1_CTL_D = (64'h1 << BRK1_CTL);
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parameter BRK1_CTL_D = (BASE_D << BRK1_CTL);
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parameter BRK1_STAT_D = (64'h1 << BRK1_STAT);
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parameter BRK1_STAT_D = (BASE_D << BRK1_STAT);
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parameter BRK1_ADDR0_D = (64'h1 << BRK1_ADDR0);
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parameter BRK1_ADDR0_D = (BASE_D << BRK1_ADDR0);
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parameter BRK1_ADDR1_D = (64'h1 << BRK1_ADDR1);
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parameter BRK1_ADDR1_D = (BASE_D << BRK1_ADDR1);
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`endif
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`endif
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`ifdef DBG_HWBRK_2
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`ifdef DBG_HWBRK_2
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parameter BRK2_CTL_D = (64'h1 << BRK2_CTL);
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parameter BRK2_CTL_D = (BASE_D << BRK2_CTL);
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parameter BRK2_STAT_D = (64'h1 << BRK2_STAT);
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parameter BRK2_STAT_D = (BASE_D << BRK2_STAT);
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parameter BRK2_ADDR0_D = (64'h1 << BRK2_ADDR0);
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parameter BRK2_ADDR0_D = (BASE_D << BRK2_ADDR0);
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parameter BRK2_ADDR1_D = (64'h1 << BRK2_ADDR1);
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parameter BRK2_ADDR1_D = (BASE_D << BRK2_ADDR1);
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`endif
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`endif
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`ifdef DBG_HWBRK_3
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`ifdef DBG_HWBRK_3
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parameter BRK3_CTL_D = (64'h1 << BRK3_CTL);
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parameter BRK3_CTL_D = (BASE_D << BRK3_CTL);
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parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
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parameter BRK3_STAT_D = (BASE_D << BRK3_STAT);
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parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
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parameter BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
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parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
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parameter BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
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`endif
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`endif
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// PUC is localy used as a data.
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reg [1:0] puc_sync;
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) puc_sync <= 2'b11;
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else puc_sync <= {puc_sync[0] , puc_rst};
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wire puc_s = puc_sync[1];
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//============================================================================
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//============================================================================
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// 2) REGISTER DECODER
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// 2) REGISTER DECODER
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//============================================================================
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//============================================================================
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// Select Data register during a burst
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// Select Data register during a burst
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wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
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wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
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// Register address decode
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// Register address decode
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reg [63:0] reg_dec;
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reg [NR_REG-1:0] reg_dec;
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always @(dbg_addr_in)
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always @(dbg_addr_in)
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case (dbg_addr_in)
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case (dbg_addr_in)
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CPU_ID_LO : reg_dec = CPU_ID_LO_D;
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CPU_ID_LO : reg_dec = CPU_ID_LO_D;
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CPU_ID_HI : reg_dec = CPU_ID_HI_D;
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CPU_ID_HI : reg_dec = CPU_ID_HI_D;
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CPU_CTL : reg_dec = CPU_CTL_D;
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CPU_CTL : reg_dec = CPU_CTL_D;
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| Line 257... |
Line 261... |
BRK3_CTL : reg_dec = BRK3_CTL_D;
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BRK3_CTL : reg_dec = BRK3_CTL_D;
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BRK3_STAT : reg_dec = BRK3_STAT_D;
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BRK3_STAT : reg_dec = BRK3_STAT_D;
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BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
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BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
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BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
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BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
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`endif
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`endif
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default: reg_dec = {64{1'b0}};
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// pragma coverage off
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default: reg_dec = {NR_REG{1'b0}};
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// pragma coverage on
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endcase
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_write = dbg_wr;
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wire reg_write = dbg_wr;
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wire reg_read = 1'b1;
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wire reg_read = 1'b1;
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// Read/Write vectors
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// Read/Write vectors
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wire [63:0] reg_wr = reg_dec & {64{reg_write}};
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wire [NR_REG-1:0] reg_wr = reg_dec & {NR_REG{reg_write}};
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wire [63:0] reg_rd = reg_dec & {64{reg_read}};
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wire [NR_REG-1:0] reg_rd = reg_dec & {NR_REG{reg_read}};
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//=============================================================================
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//=============================================================================
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// 3) REGISTER: CORE INTERFACE
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// 3) REGISTER: CORE INTERFACE
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//=============================================================================
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//=============================================================================
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| Line 285... |
Line 291... |
// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
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// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
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// |----------------------------+-------------------------------+------|
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// |----------------------------+-------------------------------+------|
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// | PMEM_SIZE | DMEM_SIZE | MPY |
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// | PMEM_SIZE | DMEM_SIZE | MPY |
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// -------------------------------------------------------------------
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// -------------------------------------------------------------------
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wire [2:0] cpu_version = `CPU_VERSION;
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// This register is assigned in the SFR module
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`ifdef ASIC
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wire cpu_asic = 1'b1;
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`else
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wire cpu_asic = 1'b0;
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`endif
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wire [4:0] user_version = `USER_VERSION;
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wire [6:0] per_space = (`PER_SIZE >> 9); // cpu_id_per * 512 = peripheral space size
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`ifdef MULTIPLIER
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wire mpy_info = 1'b1;
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`else
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wire mpy_info = 1'b0;
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`endif
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wire [8:0] dmem_size = (`DMEM_SIZE >> 7); // cpu_id_dmem * 128 = data memory size
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wire [5:0] pmem_size = (`PMEM_SIZE >> 10); // cpu_id_pmem * 1024 = program memory size
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wire [31:0] cpu_id = {pmem_size,
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dmem_size,
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mpy_info,
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per_space,
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user_version,
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cpu_asic,
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cpu_version};
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// CPU_CTL Register
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// CPU_CTL Register
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// 7 6 5 4 3 2 1 0
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// 7 6 5 4 3 2 1 0
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| Line 321... |
Line 305... |
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wire cpu_ctl_wr = reg_wr[CPU_CTL];
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wire cpu_ctl_wr = reg_wr[CPU_CTL];
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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`ifdef DBG_RST_BRK_EN
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`ifdef DBG_RST_BRK_EN
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if (dbg_rst) cpu_ctl <= 4'h4;
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if (dbg_rst) cpu_ctl <= 4'h6;
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`else
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`else
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if (dbg_rst) cpu_ctl <= 4'h0;
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if (dbg_rst) cpu_ctl <= 4'h2;
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`endif
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`endif
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else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
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else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
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wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
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wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
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| Line 342... |
Line 326... |
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
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// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
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//------------------------------------------------------------------------------------
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//------------------------------------------------------------------------------------
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reg [3:2] cpu_stat;
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reg [3:2] cpu_stat;
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|
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wire cpu_stat_wr = reg_wr[CPU_STAT];
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wire cpu_stat_wr = reg_wr[CPU_STAT];
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wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
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wire [3:2] cpu_stat_set = {dbg_swbrk, puc_pnd_set};
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wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
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wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
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always @ (posedge dbg_clk or posedge dbg_rst)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) cpu_stat <= 2'b00;
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if (dbg_rst) cpu_stat <= 2'b00;
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else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
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else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
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| Line 660... |
Line 644... |
wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
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wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
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|
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// Break after reset
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// Break after reset
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//--------------------------
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//--------------------------
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wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_s;
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wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_pnd_set;
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|
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// Freeze peripherals
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// Freeze peripherals
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//--------------------------
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//--------------------------
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wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
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wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
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| Line 750... |
Line 734... |
M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
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M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
|
dbg_halt_st ? M_ACCESS : M_SET_BRK;
|
dbg_halt_st ? M_ACCESS : M_SET_BRK;
|
M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
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M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
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M_ACCESS_BRK : mem_state_nxt = M_IDLE;
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M_ACCESS_BRK : mem_state_nxt = M_IDLE;
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M_ACCESS : mem_state_nxt = M_IDLE;
|
M_ACCESS : mem_state_nxt = M_IDLE;
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|
// pragma coverage off
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default : mem_state_nxt = M_IDLE;
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default : mem_state_nxt = M_IDLE;
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|
// pragma coverage on
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endcase
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endcase
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|
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// State machine
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// State machine
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always @(posedge dbg_clk or posedge dbg_rst)
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always @(posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) mem_state <= M_IDLE;
|
if (dbg_rst) mem_state <= M_IDLE;
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