OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg.v] - Diff between revs 176 and 202

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 176 Rev 202
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 103 $
// $Rev$
// $LastChangedBy: olivier.girard $
// $LastChangedBy$
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
// $LastChangedDate$
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 488... Line 488...
 
 
`else
`else
assign brk0_halt =  1'b0;
assign brk0_halt =  1'b0;
assign brk0_pnd  =  1'b0;
assign brk0_pnd  =  1'b0;
assign brk0_dout = 16'h0000;
assign brk0_dout = 16'h0000;
 
wire [15:0] UNUSED_eu_mab   =  eu_mab;
 
wire        UNUSED_eu_mb_en =  eu_mb_en;
 
wire  [1:0] UNUSED_eu_mb_wr =  eu_mb_wr;
 
wire [15:0] UNUSED_pc       =  pc;
`endif
`endif
 
 
`ifdef DBG_HWBRK_1
`ifdef DBG_HWBRK_1
// Hardware Breakpoint/Watchpoint Register read select
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
Line 812... Line 816...
    .mem_bw           (mem_bw)            // Burst byte width
    .mem_bw           (mem_bw)            // Burst byte width
);
);
 
 
`else
`else
    assign dbg_uart_txd    =  1'b1;
    assign dbg_uart_txd    =  1'b1;
 
 
 
    wire   UNUSED_dbg_uart_rxd =  dbg_uart_rxd;
 
 
 
 
  `ifdef DBG_I2C
  `ifdef DBG_I2C
  `else
  `else
    assign dbg_addr        =  6'h00;
    assign dbg_addr        =  6'h00;
    assign dbg_din         = 16'h0000;
    assign dbg_din         = 16'h0000;
    assign dbg_rd          =  1'b0;
    assign dbg_rd          =  1'b0;
Line 841... Line 849...
    .dbg_dout          (dbg_dout),          // Debug register data output
    .dbg_dout          (dbg_dout),          // Debug register data output
    .dbg_i2c_addr      (dbg_i2c_addr),      // Debug interface: I2C Address
    .dbg_i2c_addr      (dbg_i2c_addr),      // Debug interface: I2C Address
    .dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
    .dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
    .dbg_i2c_scl       (dbg_i2c_scl),       // Debug interface: I2C SCL
    .dbg_i2c_scl       (dbg_i2c_scl),       // Debug interface: I2C SCL
    .dbg_i2c_sda_in    (dbg_i2c_sda_in),    // Debug interface: I2C SDA IN
    .dbg_i2c_sda_in    (dbg_i2c_sda_in),    // Debug interface: I2C SDA IN
    .dbg_rd_rdy        (dbg_rd_rdy),        // Debug register data is ready for read
 
    .dbg_rst           (dbg_rst),           // Debug unit reset
    .dbg_rst           (dbg_rst),           // Debug unit reset
    .mem_burst         (mem_burst),         // Burst on going
    .mem_burst         (mem_burst),         // Burst on going
    .mem_burst_end     (mem_burst_end),     // End TX/RX burst
    .mem_burst_end     (mem_burst_end),     // End TX/RX burst
    .mem_burst_rd      (mem_burst_rd),      // Start TX burst
    .mem_burst_rd      (mem_burst_rd),      // Start TX burst
    .mem_burst_wr      (mem_burst_wr),      // Start RX burst
    .mem_burst_wr      (mem_burst_wr),      // Start RX burst
    .mem_bw            (mem_bw)             // Burst byte width
    .mem_bw            (mem_bw)             // Burst byte width
);
);
 
 
`else
`else
    assign dbg_i2c_sda_out =  1'b1;
    assign dbg_i2c_sda_out =  1'b1;
 
 
 
    wire [6:0] UNUSED_dbg_i2c_addr      = dbg_i2c_addr;
 
    wire [6:0] UNUSED_dbg_i2c_broadcast = dbg_i2c_broadcast;
 
    wire       UNUSED_dbg_i2c_scl       = dbg_i2c_scl;
 
    wire       UNUSED_dbg_i2c_sda_in    = dbg_i2c_sda_in;
 
    wire       UNUSED_dbg_rd_rdy        = dbg_rd_rdy;
`endif
`endif
 
 
endmodule // omsp_dbg
endmodule // omsp_dbg
 
 
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.