| Line 200... |
Line 200... |
parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
|
parameter BRK3_STAT_D = (64'h1 << BRK3_STAT);
|
parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
|
parameter BRK3_ADDR0_D = (64'h1 << BRK3_ADDR0);
|
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
|
parameter BRK3_ADDR1_D = (64'h1 << BRK3_ADDR1);
|
`endif
|
`endif
|
|
|
|
// PUC is localy used as a data.
|
|
reg [1:0] puc_sync;
|
|
always @ (posedge mclk or posedge por)
|
|
if (por) puc_sync <= 2'b11;
|
|
else puc_sync <= {puc_sync[0] , puc};
|
|
wire puc_s = puc_sync[1];
|
|
|
|
|
//============================================================================
|
//============================================================================
|
// 2) REGISTER DECODER
|
// 2) REGISTER DECODER
|
//============================================================================
|
//============================================================================
|
|
|
| Line 296... |
Line 303... |
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
|
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
|
//------------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------------
|
reg [3:2] cpu_stat;
|
reg [3:2] cpu_stat;
|
|
|
wire cpu_stat_wr = reg_wr[CPU_STAT];
|
wire cpu_stat_wr = reg_wr[CPU_STAT];
|
wire [3:2] cpu_stat_set = {dbg_swbrk, puc};
|
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_s};
|
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
|
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
|
|
|
always @ (posedge mclk or posedge por)
|
always @ (posedge mclk or posedge por)
|
if (por) cpu_stat <= 2'b00;
|
if (por) cpu_stat <= 2'b00;
|
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
|
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
|
| Line 614... |
Line 621... |
wire dbg_reset = cpu_ctl[`CPU_RST];
|
wire dbg_reset = cpu_ctl[`CPU_RST];
|
|
|
|
|
// Break after reset
|
// Break after reset
|
//--------------------------
|
//--------------------------
|
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc;
|
wire halt_rst = cpu_ctl[`RST_BRK_EN] & puc_s;
|
|
|
|
|
// Freeze peripherals
|
// Freeze peripherals
|
//--------------------------
|
//--------------------------
|
wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
|
wire dbg_freeze = dbg_halt_st & cpu_ctl[`FRZ_BRK_EN];
|
