| Line 56... |
Line 56... |
brk_reg_rd, // Hardware break/watch-point register read select
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brk_reg_rd, // Hardware break/watch-point register read select
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brk_reg_wr, // Hardware break/watch-point register write select
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brk_reg_wr, // Hardware break/watch-point register write select
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dbg_clk, // Debug unit clock
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dbg_clk, // Debug unit clock
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dbg_din, // Debug register data input
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dbg_din, // Debug register data input
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dbg_rst, // Debug unit reset
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dbg_rst, // Debug unit reset
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decode_noirq, // Frontend decode instruction
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eu_mab, // Execution-Unit Memory address bus
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eu_mab, // Execution-Unit Memory address bus
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_en, // Execution-Unit Memory bus enable
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mb_wr, // Execution-Unit Memory bus write transfer
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eu_mdb_in, // Memory data bus input
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eu_mdb_out, // Memory data bus output
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exec_done, // Execution completed
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fe_mb_en, // Frontend Memory bus enable
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pc // Program counter
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pc // Program counter
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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| Line 79... |
Line 76... |
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
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input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
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input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
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input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
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input dbg_clk; // Debug unit clock
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input dbg_clk; // Debug unit clock
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input [15:0] dbg_din; // Debug register data input
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input [15:0] dbg_din; // Debug register data input
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input dbg_rst; // Debug unit reset
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input dbg_rst; // Debug unit reset
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input decode_noirq; // Frontend decode instruction
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input [15:0] eu_mab; // Execution-Unit Memory address bus
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input eu_mb_en; // Execution-Unit Memory bus enable
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input eu_mb_en; // Execution-Unit Memory bus enable
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
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input [15:0] eu_mdb_in; // Memory data bus input
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input [15:0] eu_mdb_out; // Memory data bus output
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input exec_done; // Execution completed
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input fe_mb_en; // Frontend Memory bus enable
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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//=============================================================================
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//=============================================================================
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// 1) WIRE & PARAMETER DECLARATION
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// 1) WIRE & PARAMETER DECLARATION
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Line 211... |
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
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wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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reg fe_mb_en_buf;
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) fe_mb_en_buf <= 1'b0;
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else fe_mb_en_buf <= fe_mb_en;
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
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wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
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wire equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
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// Detect accesses
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// Detect accesses
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//---------------------------
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//---------------------------
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wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
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// Detect DATA read access
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// Detect DATA read access
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// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
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wire d_addr0_rd = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
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// before being written back. In that case, the read flag should not be set.
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wire d_addr1_rd = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
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// In general, We should here make sure no write access occures during the
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wire d_range_rd = equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
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// same instruction cycle before setting the read flag.
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reg [2:0] d_rd_trig;
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (dbg_rst) d_rd_trig <= 3'h0;
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else if (exec_done) d_rd_trig <= 3'h0;
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else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
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equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
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wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr;
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wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr;
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wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr;
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// Set flags
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// Set flags
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assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
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assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
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assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
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assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
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assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
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assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
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