| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 103 $
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// $Rev: 106 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 48... |
Line 48... |
dbg_rd, // Debug register data read
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dbg_rd, // Debug register data read
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dbg_uart_txd, // Debug interface: UART TXD
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dbg_uart_txd, // Debug interface: UART TXD
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dbg_wr, // Debug register data write
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dbg_wr, // Debug register data write
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// INPUTs
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// INPUTs
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dbg_clk, // Debug unit clock
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dbg_dout, // Debug register data output
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dbg_dout, // Debug register data output
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dbg_rd_rdy, // Debug register data is ready for read
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dbg_rd_rdy, // Debug register data is ready for read
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dbg_rst, // Debug unit reset
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dbg_uart_rxd, // Debug interface: UART RXD
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dbg_uart_rxd, // Debug interface: UART RXD
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mclk, // Main system clock
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mem_burst, // Burst on going
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mem_burst, // Burst on going
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mem_burst_end, // End TX/RX burst
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mem_burst_end, // End TX/RX burst
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mem_burst_rd, // Start TX burst
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mem_burst_rd, // Start TX burst
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mem_burst_wr, // Start RX burst
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mem_burst_wr, // Start RX burst
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mem_bw, // Burst byte width
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mem_bw // Burst byte width
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por // Power on reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [5:0] dbg_addr; // Debug register address
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output [5:0] dbg_addr; // Debug register address
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| Line 70... |
Line 70... |
output dbg_uart_txd; // Debug interface: UART TXD
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output dbg_uart_txd; // Debug interface: UART TXD
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output dbg_wr; // Debug register data write
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output dbg_wr; // Debug register data write
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|
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// INPUTs
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// INPUTs
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//=========
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//=========
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input dbg_clk; // Debug unit clock
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input [15:0] dbg_dout; // Debug register data output
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input [15:0] dbg_dout; // Debug register data output
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input dbg_rd_rdy; // Debug register data is ready for read
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input dbg_rd_rdy; // Debug register data is ready for read
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input dbg_rst; // Debug unit reset
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input dbg_uart_rxd; // Debug interface: UART RXD
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input dbg_uart_rxd; // Debug interface: UART RXD
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input mclk; // Main system clock
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input mem_burst; // Burst on going
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input mem_burst; // Burst on going
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input mem_burst_end; // End TX/RX burst
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input mem_burst_end; // End TX/RX burst
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input mem_burst_rd; // Start TX burst
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input mem_burst_rd; // Start TX burst
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input mem_burst_wr; // Start RX burst
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input mem_burst_wr; // Start RX burst
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input mem_bw; // Burst byte width
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input mem_bw; // Burst byte width
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input por; // Power on reset
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//=============================================================================
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//=============================================================================
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// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
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// 1) UART RECEIVE LINE SYNCHRONIZTION & FILTERING
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//=============================================================================
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//=============================================================================
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// Synchronize RXD input & buffer
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// Synchronize RXD input & buffer
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//--------------------------------
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//--------------------------------
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reg [3:0] rxd_sync;
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reg [3:0] rxd_sync;
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) rxd_sync <= 4'hf;
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if (dbg_rst) rxd_sync <= 4'hf;
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else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
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else rxd_sync <= {rxd_sync[2:0], dbg_uart_rxd};
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|
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// Majority decision
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// Majority decision
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//------------------------
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//------------------------
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reg rxd_maj;
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reg rxd_maj;
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| Line 102... |
Line 102... |
wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} +
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wire [1:0] rxd_maj_cnt = {1'b0, rxd_sync[1]} +
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{1'b0, rxd_sync[2]} +
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{1'b0, rxd_sync[2]} +
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{1'b0, rxd_sync[3]};
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{1'b0, rxd_sync[3]};
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wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
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wire rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) rxd_maj <= 1'b0;
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if (dbg_rst) rxd_maj <= 1'b0;
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else rxd_maj <= rxd_maj_nxt;
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else rxd_maj <= rxd_maj_nxt;
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wire rxd_s = rxd_maj;
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wire rxd_s = rxd_maj;
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wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
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wire rxd_fe = rxd_maj & ~rxd_maj_nxt;
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wire rxd_re = ~rxd_maj & rxd_maj_nxt;
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wire rxd_re = ~rxd_maj & rxd_maj_nxt;
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| Line 155... |
Line 155... |
RX_CMD;
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RX_CMD;
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default : uart_state_nxt = RX_CMD;
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default : uart_state_nxt = RX_CMD;
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endcase
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endcase
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// State machine
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// State machine
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always @(posedge mclk or posedge por)
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always @(posedge dbg_clk or posedge dbg_rst)
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if (por) uart_state <= RX_SYNC;
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if (dbg_rst) uart_state <= RX_SYNC;
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else if (xfer_done | sync_done |
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else if (xfer_done | sync_done |
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mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
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mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
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// Utility signals
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// Utility signals
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wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
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wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
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| Line 168... |
Line 168... |
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//=============================================================================
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//=============================================================================
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// 3) UART SYNCHRONIZATION
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// 3) UART SYNCHRONIZATION
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//=============================================================================
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//=============================================================================
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// After POR, the host needs to fist send a synchronization character (0x80)
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// After DBG_RST, the host needs to fist send a synchronization character (0x80)
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// If this feature doesn't work properly, it is possible to disable it by
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// If this feature doesn't work properly, it is possible to disable it by
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// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
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// commenting the DBG_UART_AUTO_SYNC define in the openMSP430.inc file.
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reg sync_busy;
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reg sync_busy;
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) sync_busy <= 1'b0;
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if (dbg_rst) sync_busy <= 1'b0;
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else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
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else if ((uart_state==RX_SYNC) & rxd_fe) sync_busy <= 1'b1;
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else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
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else if ((uart_state==RX_SYNC) & rxd_re) sync_busy <= 1'b0;
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assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
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assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
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`ifdef DBG_UART_AUTO_SYNC
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`ifdef DBG_UART_AUTO_SYNC
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reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
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reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
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if (dbg_rst) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
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else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
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else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
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`else
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`else
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
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| Line 207... |
Line 207... |
wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
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wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
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wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
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wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
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wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
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wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
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assign xfer_done = (xfer_bit==4'hb);
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assign xfer_done = (xfer_bit==4'hb);
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) xfer_bit <= 4'h0;
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if (dbg_rst) xfer_bit <= 4'h0;
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else if (txd_start | rxd_start) xfer_bit <= 4'h1;
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else if (txd_start | rxd_start) xfer_bit <= 4'h1;
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else if (xfer_done) xfer_bit <= 4'h0;
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else if (xfer_done) xfer_bit <= 4'h0;
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else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
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else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
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if (dbg_rst) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
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else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
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else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
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else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
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else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
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else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
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else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
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// Receive/Transmit buffer
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// Receive/Transmit buffer
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//-------------------------
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//-------------------------
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wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
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wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) xfer_buf <= 20'h00000;
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if (dbg_rst) xfer_buf <= 20'h00000;
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else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
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else if (dbg_rd_rdy) xfer_buf <= {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
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else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
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else if (xfer_bit_inc) xfer_buf <= xfer_buf_nxt;
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// Generate TXD output
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// Generate TXD output
|
//------------------------
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//------------------------
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reg dbg_uart_txd;
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reg dbg_uart_txd;
|
|
|
always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) dbg_uart_txd <= 1'b1;
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if (dbg_rst) dbg_uart_txd <= 1'b1;
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else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
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else if (xfer_bit_inc & tx_active) dbg_uart_txd <= xfer_buf[0];
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|
|
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//=============================================================================
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//=============================================================================
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// 5) INTERFACE TO DEBUG REGISTERS
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// 5) INTERFACE TO DEBUG REGISTERS
|
//=============================================================================
|
//=============================================================================
|
|
|
reg [5:0] dbg_addr;
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reg [5:0] dbg_addr;
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always @ (posedge mclk or posedge por)
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always @ (posedge dbg_clk or posedge dbg_rst)
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if (por) dbg_addr <= 6'h00;
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if (dbg_rst) dbg_addr <= 6'h00;
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else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
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else if (cmd_valid) dbg_addr <= xfer_buf[`DBG_UART_ADDR];
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|
|
reg dbg_bw;
|
reg dbg_bw;
|
always @ (posedge mclk or posedge por)
|
always @ (posedge dbg_clk or posedge dbg_rst)
|
if (por) dbg_bw <= 1'b0;
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if (dbg_rst) dbg_bw <= 1'b0;
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else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
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else if (cmd_valid) dbg_bw <= xfer_buf[`DBG_UART_BW];
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|
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wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
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wire dbg_din_bw = mem_burst ? mem_bw : dbg_bw;
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|
|
wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} :
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wire [15:0] dbg_din = dbg_din_bw ? {8'h00, xfer_buf[18:11]} :
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