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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg_uart.v] - Diff between revs 111 and 136

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Line 1... Line 1...
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
// Copyright (C) 2009 , Olivier Girard
//
//
// This source file may be used and distributed without restriction provided
// Redistribution and use in source and binary forms, with or without
// that this copyright statement is not removed from the file and that any
// modification, are permitted provided that the following conditions
// derivative work contains the original copyright notice and the associated
// are met:
// disclaimer.
//     * Redistributions of source code must retain the above copyright
 
//       notice, this list of conditions and the following disclaimer.
 
//     * Redistributions in binary form must reproduce the above copyright
 
//       notice, this list of conditions and the following disclaimer in the
 
//       documentation and/or other materials provided with the distribution.
 
//     * Neither the name of the authors nor the names of its contributors
 
//       may be used to endorse or promote products derived from this software
 
//       without specific prior written permission.
//
//
// This source file is free software; you can redistribute it and/or modify
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// it under the terms of the GNU Lesser General Public License as published
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// by the Free Software Foundation; either version 2.1 of the License, or
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// (at your option) any later version.
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
//
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// This source is distributed in the hope that it will be useful, but WITHOUT
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// License for more details.
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// You should have received a copy of the GNU Lesser General Public License
// THE POSSIBILITY OF SUCH DAMAGE
// along with this source; if not, write to the Free Software Foundation,
 
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//
//
// *File Name: omsp_dbg_uart.v
// *File Name: omsp_dbg_uart.v
// 
// 
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    wire uart_rxd_n;
    wire uart_rxd_n;
 
 
    omsp_sync_cell sync_cell_uart_rxd (
    omsp_sync_cell sync_cell_uart_rxd (
        .data_out (uart_rxd_n),
        .data_out (uart_rxd_n),
        .clk      (dbg_clk),
 
        .data_in  (~dbg_uart_rxd),
        .data_in  (~dbg_uart_rxd),
 
        .clk       (dbg_clk),
        .rst      (dbg_rst)
        .rst      (dbg_rst)
    );
    );
    wire uart_rxd = ~uart_rxd_n;
    wire uart_rxd = ~uart_rxd_n;
`else
`else
    wire uart_rxd = dbg_uart_rxd;
    wire uart_rxd = dbg_uart_rxd;
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// Majority decision
// Majority decision
//------------------------
//------------------------
reg        rxd_maj;
reg        rxd_maj;
 
 
wire [1:0] rxd_maj_cnt = {1'b0, uart_rxd}   +
wire       rxd_maj_nxt = (uart_rxd   & rxd_buf[0]) |
                         {1'b0, rxd_buf[0]} +
                         (uart_rxd   & rxd_buf[1]) |
                         {1'b0, rxd_buf[1]};
                         (rxd_buf[0] & rxd_buf[1]);
wire       rxd_maj_nxt = (rxd_maj_cnt>=2'b10);
 
 
 
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst) rxd_maj <=  1'b0;
  if (dbg_rst) rxd_maj <=  1'b1;
  else         rxd_maj <=  rxd_maj_nxt;
  else         rxd_maj <=  rxd_maj_nxt;
 
 
wire rxd_s  =  rxd_maj;
wire rxd_s  =  rxd_maj;
wire rxd_fe =  rxd_maj & ~rxd_maj_nxt;
wire rxd_fe =  rxd_maj & ~rxd_maj_nxt;
wire rxd_re = ~rxd_maj &  rxd_maj_nxt;
wire rxd_re = ~rxd_maj &  rxd_maj_nxt;
 
wire rxd_edge =  rxd_maj ^  rxd_maj_nxt;
 
 
//=============================================================================
//=============================================================================
// 2)  UART STATE MACHINE
// 2)  UART STATE MACHINE
//=============================================================================
//=============================================================================
 
 
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reg  [2:0] uart_state_nxt;
reg  [2:0] uart_state_nxt;
 
 
wire       sync_done;
wire       sync_done;
wire       xfer_done;
wire       xfer_done;
reg [19:0] xfer_buf;
reg [19:0] xfer_buf;
 
wire [19:0] xfer_buf_nxt;
 
 
// State machine definition
// State machine definition
parameter  RX_SYNC  = 3'h0;
parameter  RX_SYNC  = 3'h0;
parameter  RX_CMD   = 3'h1;
parameter  RX_CMD   = 3'h1;
parameter  RX_DATA1 = 3'h2;
parameter  RX_DATA1 = 3'h2;
parameter  RX_DATA2 = 3'h3;
parameter  RX_DATA2 = 3'h3;
parameter  TX_DATA1 = 3'h4;
parameter  TX_DATA1 = 3'h4;
parameter  TX_DATA2 = 3'h5;
parameter  TX_DATA2 = 3'h5;
 
 
// State transition
// State transition
always @(uart_state or xfer_buf or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
always @(uart_state or xfer_buf_nxt or mem_burst or mem_burst_wr or mem_burst_rd or mem_burst_end or mem_bw)
  case (uart_state)
  case (uart_state)
    RX_SYNC  : uart_state_nxt =  RX_CMD;
    RX_SYNC  : uart_state_nxt =  RX_CMD;
    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
    RX_CMD   : uart_state_nxt =  mem_burst_wr                ?
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                 mem_burst_rd                ?
                                 mem_burst_rd                ?
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                (xfer_buf[`DBG_UART_WR]      ?
                                (xfer_buf_nxt[`DBG_UART_WR]  ?
                                (xfer_buf[`DBG_UART_BW]      ? RX_DATA2 : RX_DATA1) :
                                (xfer_buf_nxt[`DBG_UART_BW]  ? RX_DATA2 : RX_DATA1) :
                                (xfer_buf[`DBG_UART_BW]      ? TX_DATA2 : TX_DATA1));
                                (xfer_buf_nxt[`DBG_UART_BW]  ? TX_DATA2 : TX_DATA1));
    RX_DATA1 : uart_state_nxt =  RX_DATA2;
    RX_DATA1 : uart_state_nxt =  RX_DATA2;
    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
    RX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                (mem_bw                      ? RX_DATA2 : RX_DATA1) :
                                 RX_CMD;
                                 RX_CMD;
    TX_DATA1 : uart_state_nxt =  TX_DATA2;
    TX_DATA1 : uart_state_nxt =  TX_DATA2;
    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
    TX_DATA2 : uart_state_nxt = (mem_burst & ~mem_burst_end) ?
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                (mem_bw                      ? TX_DATA2 : TX_DATA1) :
                                 RX_CMD;
                                 RX_CMD;
 
  // pragma coverage off
    default  : uart_state_nxt =  RX_CMD;
    default  : uart_state_nxt =  RX_CMD;
 
  // pragma coverage on
  endcase
  endcase
 
 
// State machine
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
always @(posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                          uart_state <= RX_SYNC;
  if (dbg_rst)                          uart_state <= RX_SYNC;
  else if (xfer_done    | sync_done |
  else if (xfer_done    | sync_done |
           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
           mem_burst_wr | mem_burst_rd) uart_state <= uart_state_nxt;
 
 
// Utility signals
// Utility signals
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
wire cmd_valid = (uart_state==RX_CMD) & xfer_done;
 
wire rx_active = (uart_state==RX_DATA1) | (uart_state==RX_DATA2) | (uart_state==RX_CMD);
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
wire tx_active = (uart_state==TX_DATA1) | (uart_state==TX_DATA2);
 
 
 
 
//=============================================================================
//=============================================================================
// 3)  UART SYNCHRONIZATION
// 3)  UART SYNCHRONIZATION
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`ifdef DBG_UART_AUTO_SYNC
`ifdef DBG_UART_AUTO_SYNC
 
 
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)        sync_cnt <=  {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
  if (dbg_rst)        sync_cnt <=  {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
  else if (sync_busy) sync_cnt <=  sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
  else if (sync_busy | (~sync_busy & sync_cnt[2])) sync_cnt <=  sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
 
 
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
`else
`else
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
`endif
`endif
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reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
 
 
wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire       txd_start    = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire       rxd_start    = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
wire       xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
assign     xfer_done    = (xfer_bit==4'hb);
assign     xfer_done    = rx_active ? (xfer_bit==4'ha) : (xfer_bit==4'hb);
 
 
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       xfer_bit <=  4'h0;
  if (dbg_rst)                       xfer_bit <=  4'h0;
  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
  else if (txd_start | rxd_start)    xfer_bit <=  4'h1;
  else if (xfer_done)                xfer_bit <=  4'h0;
  else if (xfer_done)                xfer_bit <=  4'h0;
  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;
  else if (xfer_bit_inc)             xfer_bit <=  xfer_bit+4'h1;
 
 
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)                       xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1'b0}};
  if (dbg_rst)                       xfer_cnt <=  {`DBG_UART_XFER_CNT_W{1'b0}};
  else if (rxd_start)                xfer_cnt <=  {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
  else if (rx_active & rxd_edge)     xfer_cnt <=  {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
  else if (txd_start | xfer_bit_inc) xfer_cnt <=  bit_cnt_max;
  else                               xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
  else if (|xfer_cnt)                xfer_cnt <=  xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
 
 
 
 
// Receive/Transmit buffer
// Receive/Transmit buffer
//-------------------------
//-------------------------
wire [19:0] xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
assign xfer_buf_nxt =  {rxd_s, xfer_buf[19:1]};
 
 
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)           xfer_buf <=  20'h00000;
  if (dbg_rst)           xfer_buf <=  20'h00000;
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
  else if (dbg_rd_rdy)   xfer_buf <=  {1'b1, dbg_dout[15:8], 2'b01, dbg_dout[7:0], 1'b0};
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
  else if (xfer_bit_inc) xfer_buf <=  xfer_buf_nxt;
Line 263... Line 271...
//=============================================================================
//=============================================================================
 
 
reg [5:0] dbg_addr;
reg [5:0] dbg_addr;
 always @ (posedge dbg_clk or posedge dbg_rst)
 always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)        dbg_addr <=  6'h00;
  if (dbg_rst)        dbg_addr <=  6'h00;
  else if (cmd_valid) dbg_addr <=  xfer_buf[`DBG_UART_ADDR];
  else if (cmd_valid) dbg_addr <=  xfer_buf_nxt[`DBG_UART_ADDR];
 
 
reg       dbg_bw;
reg       dbg_bw;
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)        dbg_bw   <=  1'b0;
  if (dbg_rst)        dbg_bw   <=  1'b0;
  else if (cmd_valid) dbg_bw   <=  xfer_buf[`DBG_UART_BW];
  else if (cmd_valid) dbg_bw   <=  xfer_buf_nxt[`DBG_UART_BW];
 
 
wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;
wire        dbg_din_bw =  mem_burst  ? mem_bw : dbg_bw;
 
 
wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf[18:11]} :
wire [15:0] dbg_din    =  dbg_din_bw ? {8'h00,           xfer_buf_nxt[18:11]} :
                                       {xfer_buf[18:11], xfer_buf[8:1]};
                                       {xfer_buf_nxt[18:11], xfer_buf_nxt[9:2]};
wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
wire        dbg_wr     = (xfer_done & (uart_state==RX_DATA2));
wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
wire        dbg_rd     = mem_burst ? (xfer_done & (uart_state==TX_DATA2)) :
                                     (cmd_valid & ~xfer_buf[`DBG_UART_WR]) | mem_burst_rd;
                                     (cmd_valid & ~xfer_buf_nxt[`DBG_UART_WR]) | mem_burst_rd;
 
 
 
 
 
 
endmodule // omsp_dbg_uart
endmodule // omsp_dbg_uart
 
 

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