| Line 53... |
Line 53... |
inst_bw, // Decoded Inst: byte width
|
inst_bw, // Decoded Inst: byte width
|
inst_dest, // Decoded Inst: destination (one hot)
|
inst_dest, // Decoded Inst: destination (one hot)
|
inst_dext, // Decoded Inst: destination extended instruction word
|
inst_dext, // Decoded Inst: destination extended instruction word
|
inst_irq_rst, // Decoded Inst: Reset interrupt
|
inst_irq_rst, // Decoded Inst: Reset interrupt
|
inst_jmp, // Decoded Inst: Conditional jump
|
inst_jmp, // Decoded Inst: Conditional jump
|
|
inst_mov, // Decoded Inst: mov instruction
|
inst_sext, // Decoded Inst: source extended instruction word
|
inst_sext, // Decoded Inst: source extended instruction word
|
inst_so, // Decoded Inst: Single-operand arithmetic
|
inst_so, // Decoded Inst: Single-operand arithmetic
|
inst_src, // Decoded Inst: source (one hot)
|
inst_src, // Decoded Inst: source (one hot)
|
inst_type, // Decoded Instruction type
|
inst_type, // Decoded Instruction type
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
irq_acc, // Interrupt request accepted (one-hot signal)
|
| Line 94... |
Line 95... |
output inst_bw; // Decoded Inst: byte width
|
output inst_bw; // Decoded Inst: byte width
|
output [15:0] inst_dest; // Decoded Inst: destination (one hot)
|
output [15:0] inst_dest; // Decoded Inst: destination (one hot)
|
output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
|
output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
|
output inst_irq_rst; // Decoded Inst: Reset interrupt
|
output inst_irq_rst; // Decoded Inst: Reset interrupt
|
output [7:0] inst_jmp; // Decoded Inst: Conditional jump
|
output [7:0] inst_jmp; // Decoded Inst: Conditional jump
|
|
output inst_mov; // Decoded Inst: mov instruction
|
output [15:0] inst_sext; // Decoded Inst: source extended instruction word
|
output [15:0] inst_sext; // Decoded Inst: source extended instruction word
|
output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
|
output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
|
output [15:0] inst_src; // Decoded Inst: source (one hot)
|
output [15:0] inst_src; // Decoded Inst: source (one hot)
|
output [2:0] inst_type; // Decoded Instruction type
|
output [2:0] inst_type; // Decoded Instruction type
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
|
| Line 419... |
Line 421... |
// 12'b100000000000: AND
|
// 12'b100000000000: AND
|
|
|
wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
|
wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
|
wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
|
wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
|
|
|
|
reg inst_mov;
|
|
always @(posedge mclk or posedge puc)
|
|
if (puc) inst_mov <= 1'b0;
|
|
else if (decode) inst_mov <= inst_to_nxt[`MOV];
|
|
|
|
|
//
|
//
|
// 4.5) SOURCE AND DESTINATION REGISTERS
|
// 4.5) SOURCE AND DESTINATION REGISTERS
|
//---------------------------------------
|
//---------------------------------------
|
|
|
