| Line 121... |
Line 121... |
input puc; // Main system reset
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input puc; // Main system reset
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input wdt_irq; // Watchdog-timer interrupt
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input wdt_irq; // Watchdog-timer interrupt
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//=============================================================================
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//=============================================================================
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// 0) UTILITY FUNCTIONS
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//=============================================================================
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// 16 bits one-hot decoder
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function [15:0] one_hot16;
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input [3:0] binary;
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begin
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one_hot16 = 16'h0000;
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one_hot16[binary] = 1'b1;
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end
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endfunction
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// 8 bits one-hot decoder
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function [7:0] one_hot8;
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input [2:0] binary;
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begin
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one_hot8 = 8'h00;
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one_hot8[binary] = 1'b1;
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end
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endfunction
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//=============================================================================
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// 1) FRONTEND STATE MACHINE
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// 1) FRONTEND STATE MACHINE
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//=============================================================================
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//=============================================================================
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// The wire "conv" is used as state bits to calculate the next response
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// The wire "conv" is used as state bits to calculate the next response
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reg [2:0] i_state;
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reg [2:0] i_state;
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| Line 226... |
Line 249... |
irq[0] ? 4'h0 : 4'hf;
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irq[0] ? 4'h0 : 4'hf;
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wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0};
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wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0};
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// Interrupt request accepted
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// Interrupt request accepted
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wire [15:0] irq_acc_all = (16'h0001 << irq_num) & {16{(i_state==I_IRQ_FETCH)}};
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wire [15:0] irq_acc_all = one_hot16(irq_num) & {16{(i_state==I_IRQ_FETCH)}};
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wire [13:0] irq_acc = irq_acc_all[13:0];
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wire [13:0] irq_acc = irq_acc_all[13:0];
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wire nmi_acc = irq_acc_all[14];
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wire nmi_acc = irq_acc_all[14];
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//=============================================================================
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//=============================================================================
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| Line 255... |
Line 278... |
else pc <= pc_nxt;
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else pc <= pc_nxt;
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// Check if ROM has been busy in order to retry ROM access
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// Check if ROM has been busy in order to retry ROM access
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reg pmem_busy;
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reg pmem_busy;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) pmem_busy <= 16'h0000;
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if (puc) pmem_busy <= 1'b0;
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else pmem_busy <= fe_pmem_wait;
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else pmem_busy <= fe_pmem_wait;
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// Memory interface
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// Memory interface
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wire [15:0] mab = pc_nxt;
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wire [15:0] mab = pc_nxt;
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wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
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wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
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| Line 345... |
Line 368... |
// 8'b00100000: CALL
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// 8'b00100000: CALL
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// 8'b01000000: RETI
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// 8'b01000000: RETI
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// 8'b10000000: IRQ
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// 8'b10000000: IRQ
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reg [7:0] inst_so;
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reg [7:0] inst_so;
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wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : ((8'h01<<ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
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wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : (one_hot8(ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) inst_so <= 8'h00;
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if (puc) inst_so <= 8'h00;
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else if (decode) inst_so <= inst_so_nxt;
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else if (decode) inst_so <= inst_so_nxt;
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| Line 370... |
Line 393... |
reg [2:0] inst_jmp_bin;
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reg [2:0] inst_jmp_bin;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) inst_jmp_bin <= 3'h0;
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if (puc) inst_jmp_bin <= 3'h0;
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else if (decode) inst_jmp_bin <= ir[12:10];
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else if (decode) inst_jmp_bin <= ir[12:10];
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wire [7:0] inst_jmp = (8'h01<<inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
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wire [7:0] inst_jmp = one_hot8(inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
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//
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//
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// 4.4) OPCODE: TWO-OPERAND ARITHMETIC
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// 4.4) OPCODE: TWO-OPERAND ARITHMETIC
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//-------------------------------------
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//-------------------------------------
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| Line 391... |
Line 414... |
// 12'b000100000000: BIC
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// 12'b000100000000: BIC
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// 12'b001000000000: BIS
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// 12'b001000000000: BIS
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// 12'b010000000000: XOR
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// 12'b010000000000: XOR
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// 12'b100000000000: AND
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// 12'b100000000000: AND
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wire [15:0] inst_to_1hot = (16'h0001<<ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
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wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
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wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
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wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
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//
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//
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// 4.5) SOURCE AND DESTINATION REGISTERS
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// 4.5) SOURCE AND DESTINATION REGISTERS
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| Line 405... |
Line 428... |
reg [3:0] inst_dest_bin;
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reg [3:0] inst_dest_bin;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) inst_dest_bin <= 4'h0;
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if (puc) inst_dest_bin <= 4'h0;
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else if (decode) inst_dest_bin <= ir[3:0];
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else if (decode) inst_dest_bin <= ir[3:0];
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wire [15:0] inst_dest = dbg_halt_st ? (16'h0001 << dbg_reg_sel) :
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wire [15:0] inst_dest = dbg_halt_st ? one_hot16(dbg_reg_sel) :
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inst_type[`INST_JMP] ? 16'h0001 :
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inst_type[`INST_JMP] ? 16'h0001 :
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inst_so[`IRQ] |
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inst_so[`IRQ] |
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inst_so[`PUSH] |
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inst_so[`PUSH] |
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inst_so[`CALL] ? 16'h0002 :
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inst_so[`CALL] ? 16'h0002 :
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(16'h0001 << inst_dest_bin);
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one_hot16(inst_dest_bin);
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// Source register
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// Source register
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reg [3:0] inst_src_bin;
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reg [3:0] inst_src_bin;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) inst_src_bin <= 4'h0;
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if (puc) inst_src_bin <= 4'h0;
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else if (decode) inst_src_bin <= ir[11:8];
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else if (decode) inst_src_bin <= ir[11:8];
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wire [15:0] inst_src = inst_type[`INST_TO] ? (16'h0001 << inst_src_bin) :
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wire [15:0] inst_src = inst_type[`INST_TO] ? one_hot16(inst_src_bin) :
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inst_so[`RETI] ? 16'h0002 :
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inst_so[`RETI] ? 16'h0002 :
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inst_so[`IRQ] ? 16'h0001 :
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inst_so[`IRQ] ? 16'h0001 :
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inst_type[`INST_SO] ? (16'h0001 << inst_dest_bin) : 16'h0000;
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inst_type[`INST_SO] ? one_hot16(inst_dest_bin) : 16'h0000;
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//
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//
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// 4.6) SOURCE ADDRESSING MODES
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// 4.6) SOURCE ADDRESSING MODES
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//--------------------------------
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//--------------------------------
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