| Line 29... |
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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 106 $
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// $Rev: 103 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-25 23:01:03 +0100 (Fri, 25 Mar 2011) $
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// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 74... |
Line 74... |
fe_mab, // Frontend Memory address bus
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fe_mab, // Frontend Memory address bus
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fe_mb_en, // Frontend Memory bus enable
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fe_mb_en, // Frontend Memory bus enable
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mclk, // Main system clock
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mclk, // Main system clock
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per_dout, // Peripheral data output
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per_dout, // Peripheral data output
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pmem_dout, // Program Memory data output
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pmem_dout, // Program Memory data output
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puc // Main system reset
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puc_rst // Main system reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output [15:0] dbg_mem_din; // Debug unit Memory data input
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output [15:0] dbg_mem_din; // Debug unit Memory data input
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| Line 87... |
Line 87... |
output [15:0] dmem_din; // Data Memory data input
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output [15:0] dmem_din; // Data Memory data input
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [1:0] dmem_wen; // Data Memory write enable (low active)
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output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
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output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
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output [15:0] fe_mdb_in; // Frontend Memory data bus input
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output [15:0] fe_mdb_in; // Frontend Memory data bus input
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output fe_pmem_wait; // Frontend wait for Instruction fetch
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output fe_pmem_wait; // Frontend wait for Instruction fetch
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output [7:0] per_addr; // Peripheral address
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output [13:0] per_addr; // Peripheral address
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output [15:0] per_din; // Peripheral data input
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output [15:0] per_din; // Peripheral data input
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output [1:0] per_we; // Peripheral write enable (high active)
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output [1:0] per_we; // Peripheral write enable (high active)
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output per_en; // Peripheral enable (high active)
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output per_en; // Peripheral enable (high active)
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output [`PMEM_MSB:0] pmem_addr; // Program Memory address
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output pmem_cen; // Program Memory chip enable (low active)
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output pmem_cen; // Program Memory chip enable (low active)
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| Line 113... |
Line 113... |
input [14:0] fe_mab; // Frontend Memory address bus
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input [14:0] fe_mab; // Frontend Memory address bus
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input fe_mb_en; // Frontend Memory bus enable
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input fe_mb_en; // Frontend Memory bus enable
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [15:0] per_dout; // Peripheral data output
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input [15:0] per_dout; // Peripheral data output
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input [15:0] pmem_dout; // Program Memory data output
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input [15:0] pmem_dout; // Program Memory data output
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input puc; // Main system reset
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input puc_rst; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) DECODER
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// 1) DECODER
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//=============================================================================
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//=============================================================================
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//------------------
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//------------------
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// Execution unit access
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// Execution unit access
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wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
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wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
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(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
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(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
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wire [15:0] eu_dmem_addr = eu_mab-(`DMEM_BASE>>1);
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wire [15:0] eu_dmem_addr = {1'b0, eu_mab}-(`DMEM_BASE>>1);
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// Debug interface access
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// Debug interface access
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wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
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wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
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(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
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(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
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wire [15:0] dbg_dmem_addr = dbg_mem_addr[15:1]-(`DMEM_BASE>>1);
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wire [15:0] dbg_dmem_addr = {1'b0, dbg_mem_addr[15:1]}-(`DMEM_BASE>>1);
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// RAM Interface
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// RAM Interface
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wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
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wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
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wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
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wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
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| Line 155... |
Line 155... |
wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
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wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
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wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
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wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
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// Debug interface access
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// Debug interface access
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wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
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wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
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wire [15:0] dbg_pmem_addr = dbg_mem_addr[15:1]-(PMEM_OFFSET>>1);
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wire [15:0] dbg_pmem_addr = {1'b0, dbg_mem_addr[15:1]}-(PMEM_OFFSET>>1);
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// ROM Interface (Execution unit has priority)
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// ROM Interface (Execution unit has priority)
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wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
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wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
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~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
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~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
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| Line 170... |
Line 170... |
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
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wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
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// Peripherals
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// Peripherals
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//--------------------
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//--------------------
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wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00);
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wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:`PER_AWIDTH+1]=={15-`PER_AWIDTH{1'b0}});
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wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00);
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wire eu_per_en = eu_mb_en & (eu_mab[14:`PER_AWIDTH] =={15-`PER_AWIDTH{1'b0}});
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wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
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wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
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wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
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wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
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wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
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wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
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wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
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wire [`PER_MSB:0] per_addr_mux = dbg_mem_en ? dbg_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
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wire [14:0] per_addr_ful = {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
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wire [13:0] per_addr = per_addr_ful[13:0];
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reg [15:0] per_dout_val;
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reg [15:0] per_dout_val;
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc_rst)
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if (puc) per_dout_val <= 16'h0000;
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if (puc_rst) per_dout_val <= 16'h0000;
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else per_dout_val <= per_dout;
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else per_dout_val <= per_dout;
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// Frontend data Mux
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// Frontend data Mux
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//---------------------------------
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//---------------------------------
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// Whenever the frontend doesn't access the ROM, backup the data
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// Whenever the frontend doesn't access the ROM, backup the data
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// Detect whenever the data should be backuped and restored
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// Detect whenever the data should be backuped and restored
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reg fe_pmem_cen_dly;
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reg fe_pmem_cen_dly;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) fe_pmem_cen_dly <= 1'b0;
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if (puc_rst) fe_pmem_cen_dly <= 1'b0;
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else fe_pmem_cen_dly <= fe_pmem_cen;
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else fe_pmem_cen_dly <= fe_pmem_cen;
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wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
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wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
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wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
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wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
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reg [15:0] pmem_dout_bckup;
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reg [15:0] pmem_dout_bckup;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) pmem_dout_bckup <= 16'h0000;
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if (puc_rst) pmem_dout_bckup <= 16'h0000;
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else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
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else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
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// Mux between the ROM data and the backup
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// Mux between the ROM data and the backup
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reg pmem_dout_bckup_sel;
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reg pmem_dout_bckup_sel;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) pmem_dout_bckup_sel <= 1'b0;
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if (puc_rst) pmem_dout_bckup_sel <= 1'b0;
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else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
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else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
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else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
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else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
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assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
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assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
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| Line 217... |
Line 219... |
// Execution-Unit data Mux
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// Execution-Unit data Mux
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//---------------------------------
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//---------------------------------
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// Select between peripherals, RAM and ROM
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// Select between peripherals, RAM and ROM
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reg [1:0] eu_mdb_in_sel;
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reg [1:0] eu_mdb_in_sel;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) eu_mdb_in_sel <= 2'b00;
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if (puc_rst) eu_mdb_in_sel <= 2'b00;
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else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
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else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
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// Mux
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// Mux
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assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
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assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
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eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
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eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
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| Line 231... |
Line 233... |
//---------------------------------
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//---------------------------------
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|
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// Select between peripherals, RAM and ROM
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// Select between peripherals, RAM and ROM
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`ifdef DBG_EN
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`ifdef DBG_EN
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reg [1:0] dbg_mem_din_sel;
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reg [1:0] dbg_mem_din_sel;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) dbg_mem_din_sel <= 2'b00;
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if (puc_rst) dbg_mem_din_sel <= 2'b00;
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else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
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else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
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`else
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`else
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wire [1:0] dbg_mem_din_sel = 2'b00;
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wire [1:0] dbg_mem_din_sel = 2'b00;
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`endif
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`endif
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